Triple via chain for advanced interconnect in a memory device

A method, comprising:

• selecting, at a first portion of a memory device, a first via chain segment of one or more via chain segments of the memory device for a test operation, wherein the one or more via chain segments comprises a second via chain segment at a second portion of the memory device and a third via chain segment at a third portion of the memory device;
• testing the first portion of the memory device responsive to selecting the first via chain segment;
• and
• determining one or more errors associated with the first portion of the memory device responsive to testing the first portion of the memory device, wherein the first via chain segment, the second via chain segment, and the third via chain segment are each configured to detect physical defects including at least one of cracks, misalignments, or disconnections within respective portions of the memory device by measuring at least one of voltage or current across respective via chain segments.

A memory device comprising:

• a memory array comprising memory cells;
• and
• control logic coupled to the memory array, the control logic to:
• select, at a first portion of the memory device, a first via chain segment of one or more via chain segments of the memory device for a test operation, wherein the one or more via chain segments comprises a second via chain segment at a second portion of the memory device and a third via chain segment at a third portion of the memory device;
• test the first portion of the memory device responsive to selecting the first via chain segment;
• and
• determine one or more errors associated with the first portion of the memory device responsive to testing the first portion of the memory device, wherein the first via chain segment, the second via chain segment, and the third via chain segment are each configured to detect physical defects including at least one of cracks, misalignments, or disconnections within respective portions of the memory device by measuring at least one of voltage or current across respective via chain segments.