Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJungmin Bak, Sangkil Lee
Life of this patent
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Abstract
A memory device includes a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling a defective resistor, and an output driver including a plurality of pull-up units including a plurality of pull-up resistors and a plurality of pull-down units including a plurality of pull-down resistors. The output driver is configured to disable or enable respective pull-up resistors and pull-down resistors based on the second code, enable a subset of pull-up units from among the plurality of pull-up units including the respective pull-up resistors based on the first code, and enable a subset of pull-down unit from among the plurality of pull-down units including the respective pull-down resistors based on the first code.
Claims20
A memory device comprising:
- a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling a defective resistor;
- and
- an output driver comprising a plurality of pull-up units including a plurality of pull-up resistors and a plurality of pull-down units including a plurality of pull-down resistors, wherein respective pull-up resistors and respective pull-down resistors are configured to be disabled or enabled based on the second code,
- wherein the output driver is configured to enable, based on the first code, a subset of pull-up units from among the plurality of pull-up units including the respective enabled pull-up resistors based on the second code, and is configured to enable, based on the first code, a subset of pull-down units from among the plurality of pull-down units including the respective enabled pull-down resistors based on the second code.
A memory system comprising:
- a memory device comprising a data input and output circuit including a plurality of pull-up units and a plurality of pull-down units and configured to output data signals through a data input and output pad, and a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling at least one of a plurality of resistors included in the data input and output circuit;
- and
- a memory controller configured to receive a data signal among the data signals, determine whether the data signal indicates a defect, generate the second code responsive to determining that the data signal indicates the defect, provide the second code to the memory device, and generate and provide the first code to the memory device.
A method for operating a memory device, the method comprising:
- writing or reading test data to or from a first in, first out (FIFO) portion of the memory device;
- determining whether a data signal output by the memory device indicates a defect;
- and
- enabling one or more resistors based on a code indicating the defect among a plurality of resistors included in the memory device;
- and
- enabling a subset of pull-up units from among a plurality of pull-up units including the respective enabled one or more resistors and a subset of pull-down units from among a plurality of pull-down units including the respective enabled one or more resistors based on setting termination resistance of the memory device.
Dependencies are inferred from the claim text.