Low-power output driver for power-supply termination in memory interface applications

An output driver, comprising:

• a delay generator configured to produce a plurality of delay signals in response to an input signal;
• a pre-driver configured to produce a plurality of control signals based on the plurality of delay signals;
• and
• a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals,
• a level shifter that receives the plurality of delay signals and provides shifted delay signals,
• wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination,
• wherein the main driver includes a plurality of slices, each of the plurality of slices including a pull-up transistor coupled in series with a pull-down transistor between system voltage and a ground, wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices,
• wherein the level shifter includes an upper level shifter and a lower level shifter, the upper level shifter configured to shift voltage levels of the plurality of delay signals within a voltage level VDDA and a lower voltage level VSSREG to generate upper delay signals, and the lower level shifter configured to shift voltage levels of the plurality of delay signals within a voltage level VDDREG and a lower voltage VSSA to generate lower delay signals;
• wherein the pre-driver includes a plurality of upper-level pre-drivers operating between the voltages VDDA and VSSREG in response to the upper delay signals to provide pull-up signals for each pull-up transistor in the plurality of slices, and a plurality of lower-level pre-drivers operating between the voltages VDDREG and VSSA in response to the lower delay signals to provide pull-down signals for each pull-down transistor in the plurality of slices;
• and
• wherein the series coupled pull-up transistor and pull-down transistor of each of the plurality of slices operates between VDD and VSSA.

A method of driving an output signal in a channel with an asymmetric termination, comprising:

• receiving an input signal;
• generating, in a delay generator, a plurality of delay signals in response to the input signal;
• producing, in a pre-driver, a plurality of control signals based on rising and falling edges of the plurality of delay signals;
• and
• providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
• wherein the main driver includes a plurality of slices, each slice having a pull-up transistor and a pull-down transistor coupled to the node, the pull-up transistor and pull-down transistor of the plurality of slices being driven by the plurality of control signals,
• wherein the plurality of control signals provides for an asymmetric switching sequence in the plurality of slices to provide an asymmetric response in the main driver in response to the asymmetric termination.

A method of driving an output signal in a channel with an asymmetric termination, comprising:

• receiving an input signal;
• generating, in a delay generator, a plurality of delay signals in response to the input signal;
• producing, in a pre-driver, a plurality of control signals based on the plurality of delay signals;
• and
• providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
• wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination,
• wherein the main driver includes a plurality of slices, each of the plurality of slices including a pull-up transistor coupled in series with a pull-down transistor between system voltage and a ground,
• wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices;
• level shifting, in an upper level shifter, the plurality of delay signals to be within a voltage level VDDA and a lower voltage level VSSREG to generate upper delay signals;
• level shifting, in a lower level shifter, the plurality of delay signals to be within a voltage level VDDREG and a lower voltage VSSA to generate lower delay signals;
• producing, in a plurality of upper-level pre-drivers operating between the voltages VDDA and VSSREG, pull-up signals in response to the upper delay signals for each pull-up transistor in the plurality of slices;
• producing, in a plurality of lower-level pre-drivers operating between the voltages VDDREG and VSSA, pull-down signals in response to the lower delay signals for each pull-down transistor in the plurality of slices;
• and
• wherein the series coupled pull-up transistor and pull-down transistor of each of the plurality of slices operates between VDD and VSSA.

An output driver, comprising:

• a delay generator configured to produce a plurality of delay signals in response to an input signal;
• a pre-driver configured to produce a plurality of control signals based on the plurality of delay signals;
• a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals;
• a diode pre-driver configured to provide a diode enable signal in response to a subset of the plurality of delay signals;
• and
• a diode block coupled to the node of the main driver, the diode block configured to provide current to the node during a rising edge of the output signal,
• wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination.

A method of driving an output signal in a channel with an asymmetric termination, comprising:

• receiving an input signal;
• generating, in a delay generator, a plurality of delay signals in response to the input signal;
• producing, in a pre-driver, a plurality of control signals based on the plurality of delay signals;
• and
• providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
• wherein the plurality of control signals provides for an asymmetric switching sequence in the plurality of slices to provide an asymmetric response in the main driver in response to the asymmetric termination;
• providing, in a diode pre-driver, a diode enable signal in response to a subset of the plurality of delay signals;
• and
• providing, in a diode block coupled to the node of the main driver, a current to the node during a rising edge of the output signal.