Watch clocking to improve security of low power processing systems

Abstract

A processing system including a peripheral configured to store security information and having a clock input receiving a gated clock, a watch clock generator configured to generate a watch clock that has a reduced duty cycle relative to a system clock, and clock control circuitry configured to select the system clock as the gated clock during normal operation of the peripheral and to select the watch clock as the gated clock during a low power mode of the peripheral. The watch clock generator may include a counter that counts system clock cycles and clock pulse selector, such as a modulo circuit, configured to select cycles of the system clock for generating the watch clock. For multiple peripherals, delay circuitry may skew a watch clock between two or more peripherals. Multiple watch clocks with different delayed duty cycles may be generated, each for a corresponding one of multiple groups of peripherals.

Dependencies are inferred from the claim text.