Accelerator with configurable circuit to perform different operation types

An accelerating method, applied to an accelerator,

• wherein the accelerator comprises a calculating circuit
• configured to implement an operation related to an elliptic curves algorithm,
• wherein the calculating circuit comprises a general logic circuit composed of a basic logic circuit, and
• wherein the general logic circuit is configured to perform an operation of different operation types in response to different inputs, and the accelerating method comprising:
• acquiring a target microcode instruction corresponding to a target type operation to be implemented, the target microcode instruction is generated according to the target type operation, wherein the target microcode instruction is used to indicate target input data required to perform the general logic circuit to implement the target type operation;
• parsing the target microcode instruction to obtain a parsing result corresponding to the target input data;
• and
• in response to the parsing result, controlling the calculating circuit to enable the calculating circuit to acquire the target input data and run the general logic circuit based on the target input data so as to complete the target type operation,
• wherein the accelerator is communicatively connected to a central processing unit (CPU), and the accelerating method further comprises:
• acquiring an operation program that performs the target type operation on at least one operand comprised in the operation program, and
• generating the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program,
• wherein the operation program further comprises a dot multiplication scalar and the target type operation is a dot multiplication operation on the dot multiplication scalar and the at least one operand,
• wherein the generating the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program comprises generating a plurality of target microcode instructions for implementing the dot multiplication operation according to the dot multiplication scalar and the at least one operand comprised in the operation program, and
• wherein the accelerating method further comprises executing each target microcode instruction in the plurality of target microcode instructions, so as to complete the dot multiplication operation.

A non-transitory computer-readable storage medium, wherein an accelerator in a computer comprises a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the processor, when running the computer program, is configured to:

• implement an operation related to an elliptic curves algorithm, wherein the operation related to the elliptic curves algorithm comprises a general logic operation composed of a basic logic operation, the general logic operation is to perform an operation of different operation types in response to different inputs, and the non-transitory computer-readable storage medium stores a computer program, the accelerator, when executing the computer program, is configured to:
• acquire a target microcode instruction corresponding to a target type operation to be implemented, the target microcode instruction is generated according to the target type operation, wherein the target microcode instruction is used to indicate target input data required to perform the general logic operation to implement the target type operation;
• parse the target microcode instruction to obtain a parsing result corresponding to the target input data;
• and
• in response to the parsing result, acquire the target input data and run the general logic operation based on the target input data so as to complete the target type operation;
• wherein the accelerator is communicatively connected to a central processing unit (CPU), and the accelerator or the CPU is configured to:
• acquire an operation program that performs the target type operation on at least one operand comprised in the operation program, and
• generate the target microcode instruction corresponding to the target type operation according to the target type operation based on the at least one operand comprised in the operation program;
• wherein the operation program further comprises a dot multiplication scalar and the target type operation is a dot multiplication operation on the dot multiplication scalar and the at least one operand;
• wherein the accelerator or the CPU is further configured to generate a plurality of target microcode instructions for implementing the dot multiplication operation according to the dot multiplication scalar and the at least one operand comprised in the operation program;
• and
• wherein the accelerator is further configured to execute each target microcode instruction in the plurality of target microcode instructions, so as to complete the dot multiplication operation.