Method and processor for executing target instructions
AssigneeShanghai Zhaoxin Semiconductor Co., Ltd.
InventorsWeilin Wang, Yingbing Guan, Mengchen Yang
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Abstract
A method for executing target instructions and being used in a processor includes the steps of: receiving an instruction; determining whether the received instruction is a target instruction according to an operation code of the received instruction; when the received instruction is not the target instruction, executing the received instruction in a first mode; and when the received instruction is the target instruction, simulating the execution of the target instruction according to basic decoding information of the target instruction in a second mode. The basic decoding information includes the operation code, and is stored in an internal register.
Claims20
A method for executing target instructions, used in a processor, comprising the steps of:
- receiving an instruction;
- determining whether the received instruction is a target instruction according to an operation code of the received instruction;
- when the received instruction is not the target instruction, executing the received instruction in a first mode, wherein the first mode is a system management mode;
- and
- when the received instruction is the target instruction, simulating the execution of the target instruction and checking whether the target instruction is supported according to basic decoding information of the target instruction in a second mode;
- wherein the basic decoding information comprises the operation code, and is stored in an internal register.
A processor for executing target instructions, comprising:
- an instruction monitoring unit, configured to receive an instruction, and to determine whether the received instruction is a target instruction according to an operation code of the received instruction;
- and
- an internal register;
- wherein when the received instruction is not the target instruction, the processor executes the received instruction in a first mode, and the first mode is a system management mode;
- when the received instruction is the target instruction, the processor simulates the execution of the target instruction and checks whether the target instruction is supported according to basic decoding information of the target instruction in a second mode;
- wherein the basic decoding information comprises the operation code, and is stored in the internal register.
Dependencies are inferred from the claim text.