Electronic system using a power regulator with reduced inrush current

An electronic system, comprising:

• a power regulator;
• and
• an output capacitance device, coupled between the power regulator and a load;
• wherein:
• the output capacitance device comprises a first capacitor and a second capacitor;
• when the power regulator is in a first power mode, the first capacitor and the second capacitor are both coupled to the power regulator;
• when the power regulator is in a second power mode, which uses less power than the first power mode, the first capacitor is coupled to the power regulator, and the second capacitor is disconnected from the power regulator and is protected from being discharged by the power regulator;
• and
• the power regulator comprises:
• a first power MOS transistor, having a source terminal coupled to a power voltage, and a drain terminal coupled to the first capacitor through a first output terminal of the power regulator;
• a second power MOS transistor, having a source terminal coupled to the power voltage, a gate terminal coupled to a gate terminal of the first power MOS transistor, and a drain terminal coupled to the second capacitor through a second output terminal of the power regulator;
• wherein the second power MOS transistor is turned off while the power regulator operates in the second power mode.