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US 12,690,483 B2Granted
Semiconductor chip package having internal I/O structures with modulated thickness to compensate for die/substrate warpage
AssigneeIntel Corporation
InventorsOnur Ozkan, Edvin Cetegen, Steve Cho, Nicholas S. Haehn, Jacob Vehonsky
Life of this patent
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Abstract
An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.
Claims16
An apparatus, comprising:
- a substrate;
- and
- I/O structures comprising pads and solder balls on the substrate to couple with a semiconductor chip, wherein a first subset of pads of the pads and solder balls in a first region of the substrate are thinner than a second subset of pads of the pads and solder balls in a second region of the substrate and wherein the substrate includes an embedded interconnect chip that is capable of interconnecting a first semiconductor chip on the substrate with a second semiconductor chip on the substrate.
A system comprising:
- a plurality of processing cores;
- a memory;
- a memory controller coupled between the plurality of processing cores and the memory;
- a network interface;
- and
- a second semiconductor chip, package comprising a first semiconductor chip and a semiconductor chip the semiconductor chip package comprising I/O structures, the I/O structures comprising pads and solder balls that are coupled to the first semiconductor chip, wherein a first subset of pads of the pads and solder balls are thinner than a second subset of pads of the pads and solder balls, wherein the semiconductor chip package also comprises a substrate, and wherein the substrate comprises an embedded interconnect chip that interconnects the first semiconductor chip with the second semiconductor chip.
3 more elements
Dependencies are inferred from the claim text.