Semiconductor package having semiconductor chip on wiring layers and method of fabricating the same

A semiconductor package, comprising:

• a wiring substrate;
• a semiconductor chip on the wiring substrate;
• and
• a molding layer on the wiring substrate, the molding layer covering the semiconductor chip,
• wherein the wiring substrate includes:
• dielectric patterns that are sequentially stacked;
• wiring patterns in the dielectric patterns;
• a dielectric layer covering a top surface of an uppermost one of the dielectric patterns, a thickness of the dielectric layer being less than a thickness of each of the dielectric patterns, and the thickness of the dielectric layer being in a range of about 1 μm to about 4 μm;
• an upper substrate pad on the dielectric layer;
• lower substrate pads on a bottom surface of a lowermost one of the dielectric patterns;
• and
• a protection layer on the bottom surface of the lowermost one of the dielectric patterns, the protection layer covering first portions of the lower substrate pads, and the protection layer including openings exposing second portions of the lower substrate pads,
• wherein the semiconductor chip comprises a chip pad at a bottom surface of the semiconductor chip, and
• wherein the chip pad is electrically connected to the upper substrate pad.