Semiconductor packaging method

A semiconductor packaging method, comprising:

• providing a carrier, wherein the carrier comprises an attachment region for attaching a chip and a non-attachment region located outside the attachment region;
• providing a seed layer on the carrier, wherein an orthographic projection of the seed layer on the carrier covers the carrier;
• forming a conductive column on a side of the seed layer away from the carrier based on the seed layer, wherein the conductive column is located outside the attachment region;
• forming a bonding layer, wherein a material of the bonding layer comprises an organic photosensitive material, an orthographic projection of the bonding layer on the carrier at least covers the attachment region, and the bonding layer is in a form of a film layer and uncured;
• and wherein the bonding layer is located on a side of the seed layer away from the carrier;
• the orthographic projection of the bonding layer on the carrier covers at least a part of the non-attachment region;
• and the bonding layer located in the non-attachment region covers a surface of the conductive column away from the seed layer, the bonding layer located in the non-attachment region surrounds the chip, and the orthographic projection of the bonding layer in the non-attachment region on the carrier adjoins the orthographic projection of the chip on the carrier;
• attaching the chip onto the bonding layer, wherein an orthographic projection of the chip on the carrier is located in the attachment region;
• the chip comprises a first surface and a second surface opposite to the first surface, the first surface faces toward the bonding layer, and a pad is disposed on one of the first surface and the second surface;
• irradiating the bonding layer by light, such that a part of the bonding layer with the orthographic projection on the carrier located outside the attachment region is cured;
• forming an encapsulation layer, at least covering a side surface of the chip;
• removing the cured bonding layer on a side of the conductive column away from the seed layer;
• forming a first wiring sub-structure on a side of the encapsulation layer away from the second surface;
• and
• forming a second wiring sub-structure on a side of the encapsulation layer away from the first surface;
• wherein one of the first wiring sub-structure and the second wiring sub-structure close to a front surface of the chip is electrically coupled with the pad, and the first wiring sub-structure is electrically coupled with the second wiring sub-structure through the conductive column.