Semiconductor structure for reducing RLC parasitic parameters and manufacturing method thereof

A method for manufacturing a semiconductor structure, comprising:

• providing a base;
• forming a chip stack on the base, the chip stack comprising a plurality of chips stacked in sequence in a direction perpendicular to a plane of the base, wherein each of the plurality of chips comprises a first sub-portion and a second sub-portion, a first surface of the first sub-portion is flush with a first surface of the second sub-portion, a second surface of the first sub-portion protrudes from a second surface of the second sub-portion, and the first surface of the first sub-portion and the first surface of the second sub-portion are oppositely arranged to the second surface of the first sub-portion and the second surface of the second sub-portion;
• after forming each of the plurality of chips, forming first conductive structures, wherein each of the first conductive structures comprises a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent ones of the plurality of chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and a material of the first conductive bump is same with a material of the first through-silicon via;
• and
• forming connection bumps on the second sub-portion of the chip.