Semiconductor interconnection structures and methods of forming the same

A method of forming an interconnection structure, comprising:

• forming a plurality of metallization layers over a substrate, wherein forming at least one metallization layer of the plurality of metallization layers comprises:
• forming a dielectric layer over an underlying metallization layer or the substrate;
• forming a sacrificial dielectric layer over the dielectric layer;
• forming a plurality of first openings extending through the sacrificial dielectric layer;
• extending at least one of the first openings through the dielectric layer to form a second opening configured to interconnect with the underlying metallization layer, thereby defining the dielectric layer as a second dielectric layer;
• filling the first openings and the second opening with a conductive material to simultaneously form a plurality of first conductive structures within the sacrificial dielectric layer and a second conductive structure extending vertically through the sacrificial dielectric layer and the second dielectric layer to the underlying metallization layer;
• removing the sacrificial dielectric layer to form gaps between the first conductive structures and the second conductive structure;
• and
• filling the gaps with an etching-process-free dielectric material conformally around the first conductive structures and the second conductive structure without subjecting the dielectric material to an etching process, thereby forming a first dielectric layer positioned above the second dielectric layer,
• wherein the etching-process-free dielectric material forms the first dielectric layer comprising air gaps selectively formed in spaces between adjacent first conductive structures where a pitch is smaller than a predetermined value.

A method of forming an interconnection structure, comprising:

• forming a lower conductive layer within a first dielectric layer over a substrate;
• forming an inter-level dielectric layer over the first dielectric layer;
• forming a conductive via through the inter-level dielectric layer to electrically connect the lower conductive layer and an upper conductive layer;
• forming a sacrificial dielectric layer surrounding the conductive via and the upper conductive layer;
• removing the sacrificial dielectric layer after forming the conductive via and upper conductive layer;
• annealing the interconnection structure to seal exposed surfaces of the conductive via and the upper conductive feature;
• and
• filling regions created as a result of removal of the sacrificial dielectric layer with an etching-process-free dielectric material.