Switching device with passive overcurrent protection

A switching device, comprising:

• a silicon carbide (SiC) power metal-oxide semiconductor field-effect transistor (MOSFET) having a source contact, a gate contact, a drain contact, a normal operating temperature range, and an active area;
• and
• a lateral junction field-effect transistor (JFET) that is structurally separate from the gate contact of the SiC MOSFET, monolithically integrated with the SiC power MOSFET, and positioned proximate the active area, wherein an electrically conductive short-circuit path exists between the gate contact and the source contact of the SiC power MOSFET, through the lateral JFET, when the switching device is heated above a normal operating temperature range, and the lateral JFET is configured such that a conduction of current through an N-channel region of the lateral JFET is:
• (i) less than about 1 milliamp (mA) when a temperature of the lateral JFET is within the normal operating temperature range of the SiC power MOSFET;
• and
• (ii) increases above the normal operating temperature range to at least about 10 mA to short the gate contact and the source contact of the SiC power MOSFET and thereby turn off the SiC power MOSFET during an overcurrent event.

An inverter circuit for use with a direct current (DC) voltage supply and a polyphase motor, the inverter circuit comprising:

• a positive voltage rail;
• a negative voltage rail;
• a DC link capacitor connected to the positive voltage rail and the negative voltage rail, and configured to receive a DC voltage waveform from the DC voltage supply;
• and
• a plurality of switching devices arranged in multiple switching pairs, each of the multiple switching pairs being connectable to the DC link capacitor and a corresponding phase lead of the polyphase motor, wherein each respective one of the switching devices includes a semiconductor power switch that is monolithically integrated with a temperature sensitive element (TSE), the TSE comprising a JFET that is structurally separate from a gate contact of the semiconductor power switch, and wherein an electrically conductive short-circuit path exists between the gate contact and a source contact of semiconductor power switch when the JFET is heated above a normal operating temperature range, and the JFET is configured such that conduction of an electric current through the JFET is:
• (i) negligible when a temperature of the TSE is within a normal operating temperature range of the semiconductor power switch;
• and
• (ii) increases above the normal operating temperature range to a level sufficient for turning off the semiconductor power switch, thereby protecting the semiconductor power switch during an overcurrent event.