Method of forming nanosheet field effect transistors with partial inside spacers

A method of forming a nanosheet device, the method comprising:

• providing a patterned channel stack extending in a first horizontal direction, the patterned channel stack comprising a plurality of nanosheet channel layers and a plurality of sacrificial release layers;
• forming a dummy gate over the patterned channel stack, the dummy gate extending in a second horizontal direction perpendicular to the first horizontal direction;
• forming a sidewall spacer on the dummy gate, wherein:
• the dummy gate and the sidewall spacer are disposed over the patterned channel stack and define a first portion of the patterned channel stack therebelow;
• second and third portions of the patterned channel stack are disposed:
• adjacent to and on opposite sides of the first portion of the patterned channel stack;
• and
• extending outside a boundary defined by the sidewall spacer;
• and
• the second and third portions of the patterned channel stack extend beyond outer surfaces of the sidewall spacer in the first horizontal direction;
• recessing the plurality of sacrificial release layers with respect to the plurality of nanosheet channel layers in the second portion and the third portion of the patterned channel stack;
• and
• subsequent to recessing the plurality of sacrificial release layers, removing remaining portions of the patterned channel stack that extend beyond the outer surfaces of the sidewall spacer.

A method of forming a nanosheet device, the method comprising:

• forming a gate dielectric layer on a plurality of nanosheet layers, the plurality of nanosheet layers comprising:
• a first nanosheet channel layer and a second nanosheet channel layer each comprising a first end connected to a first source/drain region and a second end connected to a second source/drain region;
• a first pair of cavity fills separating the first end of the first nanosheet channel layer from the first end of the second nanosheet channel layer;
• and
• a second pair of cavity fills separating the second end of the first nanosheet channel layer from the second end of the second nanosheet channel layer, wherein:
• the first pair of cavity fills are disposed between corners of the respective first ends of the first and second nanosheet channel layers;
• the second pair of cavity fills are disposed between corners of the respective second ends of the first and second nanosheet channel layers;
• and
• the gate dielectric layer is formed on (i) the first and second nanosheet channel layers, (ii) the first and second pairs of cavity fills, (iii) a portion of the first source/drain region between the first pair of cavity fills, and (iv) a portion of the second source/drain region between the second pair of cavity fills;
• and
• forming a work function layer on the gate dielectric layer.