Memory transistor with multiple charge storage layers
AssigneeLongitude Flash Memory Solutions Ltd.
InventorsIgor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
Life of this patent
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Abstract
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
Claims25
A memory device, comprising:
- a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, wherein the channel is oriented substantially perpendicular to a semiconductor material structure;
- a tunnel oxide layer surrounding the channel,
- a multi-layer charge trapping layer surrounding the tunnel oxide layer,
- a blocking oxide layer surrounding the multi-layer charge trapping layer;
- a gate electrode surrounding the blocking oxide layer;
- wherein the multi-layer charge trapping layer comprises a first nitride layer, a second nitride layer, and an oxide layer disposed between the first and second nitride layers;
- and
- wherein each of the first and second nitride layers have a silicon component, an oxygen component and a nitrogen component.
A memory device, comprising:
- a gate structure;
- a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, wherein the channel is vertical and oriented substantially perpendicular to a semiconductor material structure;
- and
- a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel,
- wherein the multi-layer charge trapping layer comprises a first dielectric layer, a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers, wherein the anti-tunneling layer includes an oxide layer, and wherein the first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride and wherein the blocking dielectric layer comprises a high K high dielectric.
Dependencies are inferred from the claim text.