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US 12,690,233 B2Granted
Raised source/drain oxide semiconducting thin film transistor and methods of making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGerben Doornbos, Blandine Duriez, Marcus Johannes Henricus van Dal
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Abstract
A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.
Claims22
A transistor, comprising:
- a patterned gate electrode;
- a dielectric layer located over the patterned gate electrode;
- a patterned first oxide semiconductor layer comprising a first oxide semiconductor material composition and including a central portion including a channel region and outer portions on opposing sides of the central portion comprising a lower portion of source/drain regions;
- a patterned second oxide semiconductor layer comprising an upper portion of the source/drain regions located on the outer portions of the patterned first oxide semiconductor layer, wherein a thickness of the source/drain regions is greater than a thickness of the channel region, the patterned second oxide semiconductor layer comprises a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the patterned second oxide semiconductor layer contacts the patterned first oxide semiconductor layer;
- an interconnect level dielectric material layer contacting an upper surface of the central portion of the patterned first oxide semiconductor layer at a contact location, wherein the patterned second oxide semiconductor layer is on opposing sides of the interconnect level dielectric material layer at the contact location;
- and
- a pair of metal contacts comprising:
- a bottom surface contacting an upper surface of the patterned second oxide semiconductor layer across an entire width of the patterned second oxide semiconductor layer;
- and
- an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the patterned second oxide semiconductor layer and with a sidewall of the patterned first oxide semiconductor layer, wherein a thickness of the source/drain regions comprises a combined thickness of the patterned second oxide semiconductor layer and the patterned first oxide semiconductor layer, and a ratio of the thickness of the source/drain regions to a thickness of the channel region of the patterned first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the patterned gate electrode is under the pair of metal contacts and a bottom surface of the dielectric layer contacts the interconnect level dielectric material layer under the pair of metal contacts.
7 more elements
A transistor, comprising:
- a gate electrode;
- a gate dielectric layer on the gate electrode;
- a channel region on the gate dielectric layer, comprising a central portion of a first oxide semiconductor layer, wherein the first oxide semiconductor layer comprises a first oxide semiconductor material composition;
- source/drain regions on the gate dielectric layer, comprising a pair of outer portions of the first oxide semiconductor layer on opposing sides of the central portion, and a second oxide semiconductor layer on the pair of outer portions of the first oxide semiconductor layer, wherein a thickness of the source/drain regions is greater than a thickness of the channel region, the second oxide semiconductor layer comprises a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the second oxide semiconductor layer contacts the first oxide semiconductor layer;
- an interconnect level dielectric material layer contacting an upper surface of the central portion of the first oxide semiconductor layer at a contact location, wherein the second oxide semiconductor layer is on opposing sides of the interconnect level dielectric material layer at the contact location;
- and
- a pair of metal contacts comprising:
- a bottom surface contacting an upper surface of the second oxide semiconductor layer across an entire width of the second oxide semiconductor layer;
- and
- an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the second oxide semiconductor layer and with a sidewall of the first oxide semiconductor layer, wherein a thickness of the source/drain regions comprises a combined thickness of the second oxide semiconductor layer and the first oxide semiconductor layer, and a ratio of the thickness of the source/drain regions to a thickness of the channel region of the first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the gate electrode is under the pair of metal contacts and a bottom surface of the gate dielectric layer contacts the interconnect level dielectric material layer under the pair of metal contacts.
7 more elements
A semiconductor device, comprising:
- a metal layer;
- a dielectric layer on the metal layer;
- a first oxide semiconductor layer on the dielectric layer comprising a first oxide semiconductor material composition and including a central portion and a pair of outer portions on opposing sides of the central portion;
- an interconnect level dielectric (ILD) layer contacting the central portion of the first oxide semiconductor layer at a contact location;
- a pair of second oxide semiconductor layer portions in the ILD layer on the pair of outer portions of the first oxide semiconductor layer, respectively, wherein the pair of second oxide semiconductor layer portions are on opposing sides of the ILD layer at the contact location, the pair of second oxide semiconductor layer portions comprise a second oxide semiconductor material composition different than the first oxide semiconductor material composition, and the pair of second oxide semiconductor layer portions contact the first oxide semiconductor layer;
- and
- a pair of metal contacts comprising:
- a bottom surface contacting an upper surface of the pair of second oxide semiconductor layer portions across an entire width of the pair of second oxide semiconductor layer portions;
- and
- an outer sidewall adjoining the bottom surface and aligned with an outer sidewall of the pair of second oxide semiconductor layer portions and with a sidewall of the first oxide semiconductor layer, wherein a ratio of a combined thickness of the pair of second oxide semiconductor layer portions and the first oxide semiconductor layer to a thickness of the first oxide semiconductor layer is in a range from 150:2 to 15:8, and wherein a sidewall of the metal layer is under the pair of metal contacts and a bottom surface of the dielectric layer contacts the ILD layer under the pair of metal contacts.
7 more elements
Dependencies are inferred from the claim text.