Manufacturing method of thin film transistor

A method for manufacturing a thin film transistor, comprising:

• using a mask layer as a mask to perform one or two doping processes on a semiconductor material layer to form a first lightly doped region, a second lightly doped region, a bridging region, a first intrinsic semiconductor region and a second intrinsic semiconductor region within the semiconductor material layer, wherein a doping concentration of the bridging region is greater than doping concentrations of the first lightly doped region and the second lightly doped region;
• forming an insulation layer on the first lightly doped region, the second lightly doped region, the bridging region, the first intrinsic semiconductor region and the second intrinsic semiconductor region;
• form a gate electrode material layer on the insulation layer, wherein the gate electrode material layer overlaps the first lightly doped region, the second lightly doped region and the bridging region, and the gate electrode material layer partially overlaps the first intrinsic semiconductor region and the second intrinsic semiconductor region;
• using the gate electrode material layer as a mask to perform another doping process on the first intrinsic semiconductor region and the second intrinsic semiconductor region to respectively form a first heavily doped region and a second heavily doped region within the first intrinsic semiconductor region and the second intrinsic semiconductor region;
• etching the gate electrode material layer to form a gate electrode;
• using the gate electrode as a mask to perform a still another doping process on portions of the first intrinsic semiconductor region and the second intrinsic semiconductor region that have not been doped during the another doping process to respectively form a third lightly doped region and a fourth lightly doped region within the first intrinsic semiconductor region and the second intrinsic semiconductor region, wherein the first intrinsic semiconductor region between the first lightly doped region and the third lightly doped region is a first channel region, and the second intrinsic semiconductor region between the second lightly doped region and the fourth lightly doped region is a second channel region, wherein the first lightly doped region connects the bridging region and the first channel region, and the second lightly doped region connects the bridging region and the second channel region, and doping concentrations of the first lightly doped region and the second lightly doped region are greater than doping concentrations of the first channel region and the second channel region;
• and
• forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected to the first heavily doped region and the second heavily doped region, respectively.