Semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorAkimasa Kinoshita
Life of this patent
Estimating the term…
Loading patent…
AssigneeFuji Electric Co., Ltd.
InventorAkimasa Kinoshita
Estimating the term…
N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n−-type or a p−-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.
A semiconductor device, comprising:
Dependencies are inferred from the claim text.