Multi-threshold voltage devices and associated techniques and configurations
AssigneeSony Group Corporation
InventorsJoseph M. Steigerwald, Tahir Ghani, Jenny Hu, Ian R.C. Post
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Abstract
Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
Claims22
An integrated circuit, comprising:
- a semiconductor substrate;
- a fin structure disposed on the semiconductor substrate;
- a first N-type fin-FET device comprising a first gate electrode having a first electrode material layer, the first electrode material layer having a first thickness;
- a second N-type fin-FET device comprising a second gate electrode having a second electrode material layer, the second electrode material layer having a second thickness greater than the first thickness;
- and
- a first P-type fin-FET device comprising a third gate electrode having a third electrode material layer, the third electrode material layer having a third thickness approximately equal to the second thickness, wherein
- the first electrode material layer, the second electrode material layer and the third electrode material layer have a first chemical composition,
- the first electrode material layer, the second electrode material layer and the third electrode material layer each have a U-shape in a cross-sectional view, and
- a gate dielectric is disposed between the fin structure and the first electrode material layer, between the fin structure and the second electrode material layer and between the fin structure and the third electrode material layer.
An electronic device comprising:
- a semiconductor substrate;
- a fin structure disposed on the semiconductor substrate;
- a first N-type fin-FET device comprising a first gate electrode having a first electrode material layer, the first electrode material layer having a first thickness;
- a second N-type fin-FET device comprising a second gate electrode having a second electrode material layer, the second electrode material layer having a second thickness greater than the first thickness;
- and
- a first P-type fin-FET device comprising a third gate electrode having a third electrode material layer, the third electrode material layer having a third thickness approximately equal to the second thickness, wherein
- the first electrode material layer, the second electrode material layer and the third electrode material layer have a first chemical composition,
- the first electrode material layer, the second electrode material layer and the third electrode material layer each have a U-shape in a cross-sectional view, and
- a gate dielectric is disposed between the fin structure and the first electrode material layer, between the fin structure and the second electrode material layer and between the fin structure and the third electrode material layer.
Dependencies are inferred from the claim text.