Inner spacer liner for gate-all-around device

A method of manufacturing a gate-all-around (GAA) device, the method comprising:

• precleaning a semiconductor substrate, the semiconductor substrate having a superlattice structure and a replacement metal gate formed on a top surface of the substrate, the superlattice structure comprising a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs;
• performing a single step chemical vapor deposition (CVD) process to form an amorphous silicon liner and a dielectric inner spacer within the superlattice structure, the amorphous silicon liner conformally formed along the plurality of recessed semiconductor material layers and the corresponding plurality of channel layers, the dielectric inner spacer formed directly on the amorphous silicon liner, the dielectric inner spacer adjacent a source region and a drain region;
• etching an outer portion of the inner spacer;
• and
• removing the replacement metal gate and the plurality of recessed semiconductor material layers from the semiconductor substrate, followed by etching an inner sidewall portion of the amorphous silicon liner.