Structure and formation method of semiconductor device with semiconductor nanostructures

A method for forming a semiconductor device structure, comprising:

• forming a plurality of sacrificial layers and a plurality of semiconductor layers laid out in an alternating manner over a substrate;
• patterning the sacrificial layers and the semiconductor layers to form a first fin structure and a second fin structure;
• forming a dummy gate stack extending across portions of the first fin structure and the second fin structure;
• forming gate spacers over sidewalls of the dummy gate stack, wherein the gate spacers partially cover the first fin structure and the second fin structure;
• removing the dummy gate stack to form a trench partially exposing the first fin structure and the second fin structure;
• trimming the semiconductor layers of exposed portions of the first fin structure and the second fin structure after the trench is formed, wherein each of the semiconductor layers of the first fin structure and the second fin structure has a trimmed portion and an edge portion adjacent to the trimmed portion, and the edge portion is wider than the trimmed portion;
• removing the sacrificial layers;
• and
• forming a metal gate stack wrapped around the semiconductor layers of the first fin structure and the second fin structure.

A semiconductor device structure, comprising:

• a plurality of semiconductor nanostructures;
• a gate stack wrapped around intermediate portions of the semiconductor nanostructures, wherein each of the intermediate portions has a first width measured along a lengthwise axis of the gate stack;
• and
• a gate spacer over a sidewall of the gate stack, wherein the gate spacer surrounds edge portions of the semiconductor nanostructures, each of the edge portions has a second width measured along the lengthwise axis of the gate stack, and the second width is greater than the first width.