Microelectronic devices including staircase structures, and related memory devices

A memory device, comprising:

• blocks horizontally separated from one another in a first direction by insulative slot structures and respectively including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, one of the blocks comprising:
• a stadium structure including opposing staircase structures individually having steps comprising horizontal ends of some of the tiers;
• and
• an additional stadium structure horizontally offset from the stadium structure in a second direction orthogonal to the first direction and including additional opposing staircase structures individually having additional steps comprising horizontal ends of some other of the tiers;
• conductive pads on the steps of the opposing staircase structures of the stadium structure of the one of the blocks and absent from the additional steps of the additional opposing staircase structures of the additional stadium structure of the one of the blocks;
• conductive contacts on upper surfaces of the conductive pads;
• additional conductive contacts on upper surfaces of the conductive structures of the some other of the tiers at the additional steps of the additional opposing staircase structures of the additional stadium structure of the one of the blocks;
• and
• strings of memory cells vertically extending through a portion of the one of the blocks horizontally neighboring the stadium structure in the second direction.

A 3D NAND Flash memory device, comprising:

• a stack structure including tiers respectively comprising conductive material and insulative material vertically neighboring the conductive material, the stack structure comprising:
• a memory array region;
• and
• a stair step region horizontally neighboring the memory array region and comprising:
• an upper select gate stadium structure comprising staircase structures respectively having steps comprising edges of an upper group of the tiers;
• and
• a lower select gate stadium structure comprising additional staircase structures respectively having additional steps comprising edges of a lower group of the tiers;
• conductive pad structures within the stair step region of the stack structure,
• at least some of the conductive pad structures on the steps of the staircase structures of the upper select gate stadium structure, and
• the additional steps of the additional staircase structures of the lower select gate stadium structure free of any of the conductive pad structures thereon;
• and
• vertical strings of memory cells within the memory array region of the stack structure.