Computing platform for preventing side channel attacks

A computing platform—for preventing side channel attacks comprising:

• a memory module configured for storing data of a computer program and program instructions;
• a CPU configured for executing said computer program;
• a pipeline having a plurality of stages integrated in said CPU, said plurality of stages being configurated for transferring electrical signal via an on-chip interconnect bus;
• said program instructions being decoded by one stage of said plurality of stages;
• each stage of said pipeline having at least one combinatorial module,
• said at least one combinatorial module having a plurality of data input and a plurality control input and at least a data output;
• each program instruction traveling from left to right through said pipeline, and within each stage can activate one or more or none of said at least one combinatorial module;
• wherein the pipeline comprises a plurality digital logic means interconnected to each other and configured for generating random values or program data values in a clock cycle, said plurality of digital logic means being in communication signal with said plurality of data input of said combinatorial module, so as when said program instruction enters one stage of said plurality of stages, all the combinatorial modules of said that stage that are not activated by the program instruction will have their input data fed with said random values and all the combinatorial modules of said that stage that are activated by said program instruction will have their unused data input fed with said random values and their used data inputs fed with said program data values, and
• wherein said combinatorial module comprises:
• a first Arithmetic Logic Unit module that operates on two operands and said first Arithmetic Logic Unit module is used to perform logic and arithmetic instructions, to compute the memory address for instructions, and to evaluate the condition for conditional branch instructions,
• a first mux and a second mux that are used to drive the values of the first and the second operand to said first Arithmetic Logic Unit module combinatorial module;
• a third mux that is used to drive the value to be written in the memory module;
• a second Arithmetic Logic Unit module that is used to compute the branch target address, said second Arithmetic Logic Unit module is used to change the control flow of the program;
• a Load Store Unit that is used to perform load and/or store instructions, so as to read and/or write data values, both program as well as random ones, from and to said memory;
• a fourth mux is used to select between the value produced by said ALU and the one loaded from the memory via the LSU;
• and
• a fifth mux is used to select either the output of said third mux or the data value, being either a random data or a program data one, from said write back stage.

A computing platform—for preventing side channel attacks comprising:

• a memory module configured for storing data of a computer program and program instructions;
• a CPU configured for executing said computer program;
• a pipeline having a plurality of stages integrated in said CPU, said plurality of stages being configurated for transferring electrical signal via an on-chip interconnect bus;
• said program instructions being decoded by one stage of said plurality of stages;
• each stage of said pipeline having at least one combinatorial module,
• said at least one combinatorial module having a plurality of data input and a plurality control input and at least a data output;
• each program instruction traveling from left to right through said pipeline, and within each stage can activate one or more or none of said at least one combinatorial module;
• wherein the pipeline comprises a plurality digital logic means interconnected to each other and configured for generating random values or program data values in a clock cycle, said plurality of digital logic means being in communication signal with said plurality of data input of said combinatorial module, so as when said program instruction enters one stage of said plurality of stages, all the combinatorial modules of said that stage that are not activated by the program instruction will have their input data fed with said random values and all the combinatorial modules of said that stage that are activated by said program instruction will have their unused data input fed with said random values and their used data inputs fed with said program data values, and
• wherein said plurality digital logic means are configured for generating cleaner instructions, each cleaner instruction being interleaved between each pair of program instructions that are consecutively executed, to ensure that each stage of the pipeline traversed by the cleaner instruction has its combinatorial module and memory elements fed by said random values.