Hardware optimization device and method for low-density parity check decoder

A hardware optimization device for optimizing a hardware of a low-density parity check (LDPC) decoder, comprising:

• a variable node hardware block configured to operate in a multi-stage pipeline structure for updating a variable node message delivered to each variable node;
• and
• a check node hardware block configured to operate in a multi-stage pipeline structure for updating a check node message delivered to each check node,
• wherein the variable node hardware block and the check node hardware block divide a parity check matrix into N column blocks for the update (N is a natural number of 2 or more), repeatedly perform calculations for the variable node and the check node for each of the divided column blocks, and perform different calculations for variable nodes according to respective phases each corresponding to one of the divided column blocks, through a pipeline method,
• wherein each of the respective phases comprise both the variable node calculations and the check node calculations for the corresponding column block, wherein each of the respective phases comprise a plurality of pipeline stages, wherein a first pipeline stage of an Mth respective phase (M is a natural number of 2 or more) is calculated in parallel to a second pipeline stage of an Mth−1 respective phase, and wherein the phase is divided to sequentially perform the variable node calculations and the check node calculations for the corresponding column block.