Pass gate circuit arranged for providing an input to an output based on a control signal, as well as a corresponding method and computer program product

A pass gate circuit arranged to provide an input to an output based on a control signal, the pass gate circuit comprising:

• a pass gate switch circuit comprising a P-Metal Oxide Semiconductor (PMOS), Field Effect Transistor (FET), PMOS FET, cascaded in parallel with a N-type Metal Oxide Semiconductor Field Effect Transistor (NMOS FET), wherein the pass gate switch circuit is arranged to provide the input to the output;
• a control circuit comprising two in series cascaded inverters and a first of the two inverters has an output that is provided to a gate of the PMOS FET and a second of the two inverters has an output that is provided to a gate of the NMOS FET, wherein the inverters are powered by a supply voltage;
• a failsafe circuit arranged to provide a high-impedance path in the pass gate switch circuit, between the input and the output, when the supply voltage fails, the failsafe circuit comprising:
• a failsafe inverter having an input connected to the supply voltage, and being powered by the input;
• wherein the failsafe circuit is arranged to provide the high-impedance path by controlling the gate of the PMOS FET by an output of the failsafe inverter, wherein the failsafe circuit further comprises:
• an enable PMOS FET connected to the output of the failsafe inverter and to the gate of the PMOS FET of the pass gate switch, and wherein the enable PMOS FET has a gate that is connected to the supply voltage.