Linear and bandwidth reconfigurable current buffer or amplifier

An apparatus, comprising:

• a positive input for an input differential signal;
• a negative input for the input differential signal;
• a positive output for an output differential signal;
• a negative output for the output differential signal;
• a first capacitor including a first terminal coupled to the positive output;
• a second capacitor including a first terminal coupled to the negative output;
• a switching network configured to:
• couple a second terminal of the first capacitor to the negative input or a positive node based on a mode signal;
• and
• couple a second terminal of the second capacitor to the positive input or a negative node based on the mode signal;
• a first field effect transistor (FET) including a first source, a first gate, and a first drain, wherein the first source is coupled to an upper voltage rail, and wherein the first gate is coupled to the first drain;
• a first current source coupled between the first drain and a lower voltage rail, wherein the first drain coincides with the positive input or the positive node;
• a second FET including a second source, a second gate, and a second drain, wherein the second source is coupled to the upper voltage rail, and wherein the second gate is coupled to the second drain;
• a second current source coupled between the second drain and the lower voltage rail, wherein the second drain coincides with the negative input or the negative node;
• a third FET including a third source, a third gate, and a third drain, wherein the third source is coupled to the upper voltage rail, wherein the third gate is coupled to the second gate, and wherein the third drain serves as the positive output;
• and
• a fourth FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth source is coupled to the upper voltage rail, wherein the fourth gate is coupled to the first gate, and wherein the fourth drain serves as the negative output.

An apparatus, comprising:

• a positive input for an input differential signal;
• a negative input for the input differential signal;
• a positive output for an output differential signal;
• a negative output for the output differential signal;
• a first capacitor including a first terminal coupled to the positive output;
• a second capacitor including a first terminal coupled to the negative output;
• a switching network configured to:
• couple a second terminal of the first capacitor to the negative input or a positive node based on a mode signal;
• and
• couple a second terminal of the second capacitor to the positive input or a negative node based on the mode signal;
• a first current source;
• a first field effect transistor (FET) including a first source, a first gate, and a first drain, wherein the first current source is coupled between an upper voltage rail and the first drain, wherein the first drain is coupled to the first gate, wherein the first source is coupled to a lower voltage rail, and wherein the first drain serves as the positive input or the positive node;
• a second current source;
• a second FET including a second source, a second gate, and a second drain, wherein the second current source is coupled between the upper voltage rail and the second drain, wherein the second drain is coupled to the second gate, wherein the second source is coupled to the lower voltage rail, and wherein the second drain serves as the negative input or the negative node;
• a third FET including a third source, a third gate, and a third drain, wherein the third drain serves as the positive output, wherein the third gate is coupled to the second gate, and wherein the third source is coupled to the lower voltage rail;
• and
• a fourth FET including a fourth source, a fourth gate, and a fourth drain, wherein the fourth drain serves as the negative output, wherein the fourth gate is coupled to the first gate, and wherein the fourth source is coupled to the lower voltage rail.

An apparatus, comprising:

• a positive input for an input differential signal;
• a negative input for the input differential signal;
• a positive output for an output differential signal;
• a negative output for the output differential signal;
• a first capacitor including a first terminal coupled to the positive output;
• a second capacitor including a first terminal coupled to the negative output;
• a switching network configured to:
• couple a second terminal of the first capacitor to the negative input or a positive node based on a mode signal;
• and
• couple a second terminal of the second capacitor to the positive input or a negative node based on the mode signal;
• wherein the positive node comprises a first positive node and a second positive node, wherein the negative node comprises a first negative node and a second negative node, wherein the first capacitor comprises a first set of capacitors including a first set of terminals coupled to the positive output, wherein the second capacitor comprises a second set of capacitors including a first set of terminals coupled to the negative output, and wherein the switching network is configured to:
• couple a second set of terminals of the first set of capacitors to the negative input or the first and second positive nodes, respectively, based on the mode signal;
• and
• couple a second set of terminals of the second set of capacitors to the positive input or the first and second negative nodes, respectively, based on the mode signal.

A method, comprising coupling capacitors to a differential amplifier to configure the capacitors as gate-drain neutralization capacitors in response to a mode signal indicating a high bandwidth mode;

• wherein the capacitors comprise a first capacitor and a second capacitor, and wherein coupling the capacitors to the differential amplifier to configure the capacitors as gate-drain neutralization capacitors comprises:
• coupling a first terminal of the first capacitor to a positive output of the differential amplifier;
• coupling a first terminal of the second capacitor to a negative output of the differential amplifier;
• coupling a second terminal of the first capacitor to a positive input of the differential amplifier;
• and
• coupling a second terminal of the second capacitor to a negative input of the differential amplifier.