Digitally controlled oscillator

Phase-locked loop (PLL) circuitry comprising:

• an oscillator comprising:
• a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node;
• a second plurality of capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulation capacitor bank;
• a current source;
• a first inductive element coupled to the current source and coupled between the first node and the second node;
• a negative transconductance stage coupled between the first node and the second node;
• and
• a second inductive element between the negative transconductance stage and a reference node.

A Digitally Controlled Oscillator (DCO) comprising:

• a negative transconductance stage coupled to a first node, a second node, and a reference node;
• a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting the first node to a first output node, and the second path connecting the second node to a second output node, wherein at least one of the first plurality of capacitor banks is controlled to achieve a phase lock for a phase-locked loop (PLL) that includes the DCO;
• and
• a second plurality of capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulation capacitor bank that is controlled to modulate at least one output signal of the DCO, wherein:
• the first plurality of capacitor banks includes a first capacitor bank having a first discrete step size, a second capacitor bank having a second discrete step size, and a third capacitor bank having a third discrete step size,
• the second plurality of capacitor banks includes a fine modulation capacitor bank having a fourth discrete step size and a coarse modulation capacitor bank having a fifth discrete step size,
• the first discrete step size is greater than the second discrete step size,
• the second discrete step size is greater than the fourth discrete step size,
• the fourth discrete step size is greater than the fifth discrete step size,
• the fifth discrete step size is greater than the third discrete step size, and
• the first and second pluralities of capacitor banks are arranged between the negative transconductance stage and the first and second output nodes in order of decreasing step size.