Semiconductor device and testing method for memory circuit

A semiconductor device comprising an SRAM (Static Random Access Memory) circuit operating based on an external power supply voltage,

• wherein the SRAM circuit includes:
• a memory cell array in which a plurality of memory cells including the first memory cell are arranged in a matrix form including a plurality of rows and a plurality of columns;
• a first bit line pair extending in a first direction;
• a column decoder configured to decode a column address and to select a column corresponding to the decoded column address;
• a first word line extending in a second direction intersecting with the first direction;
• a row decoder configured to decode a row address and to select a row corresponding to the decoded row address;
• a first word line driver driving the first word line;
• a first memory cell electrically connected to the first bit line pair and the first word line, wherein the first word line corresponds to one of the plurality of rows, and the first bit line pair corresponds to one of the plurality of columns;
• a first power supply line supplying an operating voltage to the first memory cell;
• a power supply voltage reduction circuit generating a reduction voltage obtained by lowering the external power supply voltage, and outputting the reduction voltage to a voltage supply line;
• the voltage supply line coupled to the first power supply voltage selection circuit and the second power supply voltage selection circuit;
• a first power supply voltage selection circuit selecting, as a drive voltage of the first word line driver, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line based on test data being written into or reading from the first memory cell;
• a second power supply voltage selection circuit selecting, as the operating voltage supplied from the first power supply line to the first memory cell, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line based on test data being written into or reading from the first memory cell;
• and
• an internal controller switching a mode of the SRAM circuit between a normal mode and a test mode by controlling the power supply voltage reduction circuit and the first and second power supply voltage selection circuits,
• wherein, in the normal mode, the internal controller causes the first power supply voltage selection circuit and the second power supply voltage selection circuit to select the external power supply voltage,
• wherein, in the test mode, the internal controller causes the first power supply voltage selection circuit to select the reduction voltage as the drive voltage of the first word line driver when writing test data into the first memory cell and to select the external power supply voltage as the drive voltage of the first word line driver when reading test data from the first memory cell, and causes the second power supply voltage selection circuit to select the external power supply voltage as the voltage supplied to the first power supply line when writing the test data and to select the reduction voltage as the voltage supplied to the first power supply line when reading the test data,
• wherein the voltage supply line is arranged between the memory cell array and the column decoder in the second direction,
• wherein the second power supply voltage selection circuit is individually arranged for each column of the memory cell array between the memory cell array and the column decoder, and
• wherein the first power supply voltage selection circuit is arranged between the memory cell array and the row decoder, and is arranged in the second direction with respect to and adjacent to the second power supply voltage selection circuit.