Back to results
US 12,688,901 B2Granted
Semiconductor device that detects connection defects between word lines and bit lines and test method for the same
AssigneeSK hynix Inc.
InventorTae Sik Yun
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a control circuit configured to deactivate a word line during an active operation during a test mode, generate a matching control signal and a sense amplifier drive signal, and activate the word line after a settling period during the test mode, and a sense amplifier configured to drive a bit line and an inverted bit line to a same voltage level based on the matching control signal during the mismatching cancellation operation, and sense and amplify a voltage difference between the bit line and the inverted bit line based on the sense amplifier drive signal when the word line is activated after the settling period during the test mode.
Claims31
A semiconductor device comprising:
- a control circuit configured to deactivate a word line during an active operation during a test mode, generate a matching control signal and a sense amplifier drive signal, and activate the word line after a settling period during the test mode;
- and
- a sense amplifier configured to drive a bit line and an inverted bit line to a same voltage level based on the matching control signal during the mismatching cancellation operation, and sense and amplify a voltage difference between the bit line and the inverted bit line based on the sense amplifier drive signal when the word line is activated after the settling period during the test mode.
A semiconductor device comprising:
- a voltage control circuit configured to generate a voltage level of a first supply voltage at a first setting level, generate a voltage level of a second supply voltage at a third setting level, and subsequently generate a voltage at a second setting level for the first supply voltage and for the second supply voltage during a mismatching cancellation operation;
- and
- a sense amplifier configured to receive the first supply voltage and the second supply voltage, to drive a bit line and an inverted bit line to a same voltage level based on a matching control signal and a sense amplifier drive signal during the mismatching cancellation operation, to receive the first supply voltage and the second supply voltage, and to sense and amplify a voltage difference between the bit line and the inverted bit line when a word line is activated after a settling period during a test mode.
A test method comprising:
- entering a test mode and deactivating a word line during a first active operation;
- performing mismatching cancellation including:
- disabling a sense amplifier drive signal, generating a first supply voltage at a first setting level, generating a second supply voltage at a third setting level, and driving a bit line and an inverted bit line to a same voltage level;
- and
- generating the first supply voltage and the second supply voltage at a second setting level, sensing and amplifying a voltage difference between the bit line and the inverted bit line when the word line is activated during a second active operation, and sensing voltage levels of the bit line and the inverted bit line to detect connection defects between the word line and the bit line.
2 more elements
A semiconductor device comprising:
- a control circuit configured to deactivate a word line from an input time of an active command to an input time of a burst command during a test mode, to generate a matching control signal and a sense amplifier drive signal, and to activate the word line after a settling period during the test mode;
- and
- a sense amplifier configured to drive a bit line and an inverted bit line to a same voltage level based on the matching control signal during a mismatching cancellation operation and to sense and amplify a voltage difference between the bit line and the inverted bit line based on the sense amplifier drive signal when the word line is activated after the settling period during the test mode.
A method comprising:
- during a first operation of a test mode, deactivating a word line and performing mismatching cancellation including generating a first supply voltage at a first setting level, generating a second supply voltage at a third setting level, and driving a bit line and an inverted bit line to a same voltage level;
- and
- during a second operation of the test mode, sensing and amplifying a voltage difference between the bit line and the inverted bit line when the word line is activated and sensing voltage levels of the bit line and the inverted bit line to detect connection defects between the word line and the bit line.
Dependencies are inferred from the claim text.