Device providing improved fail bit count operation

A memory device comprising:

• a memory cell array;
• a page buffer circuit electrically connected to the memory cell array via a bit line, wherein the page buffer circuit is configured to output a page buffer signal corresponding to a result of a verify operation with respect to a program operation;
• a page buffer decoder configured to decode the page buffer signal and output a decoding signal corresponding to fail bit information;
• a fail bit counter configured to output a count signal corresponding to a number of fail bits with respect to the program operation based on the decoding signal;
• and
• a control circuit configured to determine a program pass or a program fail of the program operation based on the count signal,
• wherein the fail bit counter comprises:
• a first current mirror circuit configured to output a first voltage corresponding to the decoding signal;
• a plurality of transistors comprising a common gate configured to receive a reference current signal, wherein ones of the plurality of transistors further comprise respective first terminals electrically connected to the first current mirror circuit, and wherein the plurality of transistors are configured to output a plurality of comparative reference current signals obtained by mirroring the reference current signal;
• a plurality of resistors respectively electrically connected to respective second terminals of the plurality of transistors;
• and
• a comparison circuit configured to determine a compared result by comparing the first voltage corresponding to the decoding signal with respective ones of a plurality of second voltages corresponding to the plurality of comparative reference current signals, and configured to output the count signal corresponding to the compared result.

A device comprising:

• a first current mirror circuit configured to receive a decoding signal according to a number of fail bits that are program-failed, and configured to output a first voltage corresponding to the decoding signal;
• a second current mirror circuit configured to output a plurality of comparative reference current signals based on a reference current signal;
• and
• a comparison circuit configured to determine a compared result by comparing the first voltage with respective ones of a plurality of second voltages corresponding to the plurality of comparative reference current signals, and configured to output a count signal corresponding to the compared result,
• wherein the second current mirror circuit comprises:
• a first transistor comprising a first terminal configured to receive the reference current signal and a second terminal electrically connected to a first resistor;
• and
• a plurality of second transistors, the plurality of second transistors comprising:
• a common gate that is electrically connected to a gate of the first transistor;
• respective third terminals through which the plurality of comparative reference current signals are configured to flow;
• and
• respective fourth terminals electrically connected to respective ones of a plurality of second resistors.