US 12,688,886 B2Granted

Method of operating phase change memories, corresponding device and computer program product

AssigneeSTMicroelectronics International N.V.

InventorsFrancesco Tomaiuolo, Marco Ruta, Michelangelo Pisasale, Marion Helne Grimal, Luigi Buono, Antonino Conte, Diego De Costantini, Marco Eugenio Gibilaro

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Abstract

A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.

Claims19

Dependent claims

A method of performing write operations in a Phase Change Memory (PCM) device, the PCM device comprising a plurality of sets of cells configured to have written therein, in response to a write operation, a binary logic level selected from a high logic level and a low logic level, wherein each cell is included in a respective set of cells in the plurality of sets of cells, the method comprising:

performing, on the cells in said plurality of sets of cells, write verify operations configured to provide results indicative of an actual logic level stored in the cells in said plurality of sets wherein the write verify operations are performed on each cell with a set of parameters selected as a function of the respective set of cells including the cell;
wherein performing write verify operations comprises:
performing first write verify operations on first cells in said plurality of sets of cells by checking if a current flowing through each first cell subjected to the first write verify operation is higher than a first reference current having a first direction of inequality;
and
performing second write verify operations on second cells in said plurality of sets of cells by checking if a current flowing through each second cell subjected to the second write verify operation is lower than a second reference current having a second direction of inequality;
checking, based on the results from said write verify operations, if the actual logic level stored in the cells in said plurality of sets matches said binary logic level;
wherein checking comprises:
determining that the actual logic level stored in the first cells in said plurality of sets of cells fails to match said binary logic level in response to the current flowing through the first cell subjected to first write verify operation being lower than the first reference current;
and
determining that the actual logic level stored in the second cells in said plurality of sets of cells fails to match said binary logic level in response to the current flowing through the second cell subjected to second write verify operation being higher than the second reference current;
and
in response to said checking determining that in at least one cell in said plurality of sets the actual logic level fails to match said binary logic level, correcting said actual logic level to match said binary logic level by performing one of:
a set write operation in case the binary logic level is a high logic level, and
a reset write operation in case the binary logic level is a low logic level.

11 more elements

A method of performing write operations in a Phase Change Memory (PCM) device wherein each bit of data is stored in a pair of memory cells comprising a direct memory cell configured to store a direct bit value equal to one of a set state and a reset state and a complementary memory cell configured to store a complementary bit value equal to the other of said set state and reset state, the method comprising, in response to writing said bit of data to the pair of memory cells:

performing a write verify operation on the pair of memory cells by:
comparing output current from only the direct memory cell of the pair of memory cells to a first reference current to detect whether the direct bit value is incorrectly in the set state;
comparing output current from only the complementary memory cell of the pair of memory cells to the first reference current to detect whether the complementary bit value is incorrectly in the set state;
comparing output current from only the direct memory cell of the pair of memory cells to a second reference current to detect whether the direct bit value is incorrectly in the reset state;
and
comparing output current from only the complementary memory cell of the pair of memory cells to the second reference current to detect whether the complementary bit value is incorrectly in the reset state;
and
selectively performing a correction to the pair of memory cells by:
when the direct bit value in the direct memory cell is detected to be incorrectly in the set state, applying a reset write operation to the direct memory cell to program the direct bit value to the reset state;
when the direct bit value in the direct memory cell is detected to be incorrectly in the reset state, applying a set write operation to the direct memory cell to program the direct bit value to the set state;
when the complementary bit value in the complementary memory cell is detected to be incorrectly in the set state, applying a reset write operation to the complementary memory cell to program the complementary bit value to the reset state;
and
when the complementary bit value in the complementary memory cell is detected to be incorrectly in the reset state, applying a set write operation to the complementary memory cell to program the complementary bit value to the set state.

10 more elements

Dependencies are inferred from the claim text.