Thyristor memory cell, thyristor memory array, and method for fabricating a thyristor memory array

A thyristor memory array, comprising:

• a plurality of first thyristor memory cells arranged in a first array that includes multiple columns and multiple rows, wherein the columns are arranged in a first direction, and the rows are arranged in a second direction that is perpendicular to the first direction;
• and
• a plurality of second thyristor memory cells arranged in a second array that is stacked over the first array and that includes multiple columns and multiple rows, wherein the columns of the second array are arranged in the first direction, and the rows of the second array are arranged in the second direction;
• wherein each of the first thyristor memory cells includes:
• a semiconductor cathode;
• a first un-doped semiconductor feature that is stacked on the semiconductor cathode in a third direction which is perpendicular to the first direction and the second direction;
• a second un-doped semiconductor feature that is stacked on the first un-doped semiconductor feature in the third direction;
• a semiconductor anode that is stacked on the second un-doped semiconductor feature in the third direction;
• and
• a gate feature that is disposed on one of the first un-doped semiconductor feature and the second un-doped semiconductor feature;
• wherein a bottom edge of a conduction band of the semiconductor anode is higher than a bottom edge of a conduction band of the first un-doped semiconductor feature, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor feature, which is higher than a bottom edge of a conduction band of the semiconductor cathode;
• wherein a top edge of a valence band of the semiconductor anode is higher than a top edge of a valence band of the first un-doped semiconductor feature, which is higher than a top edge of a valence band of the second un-doped semiconductor feature, which is higher than a top edge of a valence band of the semiconductor cathode;
• wherein each of the second thyristor memory cells includes a semiconductor anode, a first un-doped semiconductor feature, a second un-doped semiconductor feature, a semiconductor cathode and a gate feature;
• wherein, for each of the second thyristor memory cells:
• the second un-doped semiconductor feature of the second thyristor memory cell is stacked on the semiconductor anode of the second thyristor memory cell in the third direction;
• the first un-doped semiconductor feature of the second thyristor memory cell is stacked on the second un-doped semiconductor feature of the second thyristor memory cell in the third direction;
• the semiconductor cathode of the second thyristor memory cell is stacked on the first un-doped semiconductor feature of the second thyristor memory cell in the third direction;
• and
• the gate feature of the second thyristor memory cell is disposed on one of the first un-doped semiconductor feature and the second un-doped semiconductor feature of the second thyristor memory cell;
• wherein a bottom edge of a conduction band of the semiconductor anode of the second thyristor memory cell is higher than a bottom edge of a conduction band of the first un-doped semiconductor feature of the second thyristor memory cell, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor feature of the second thyristor memory cell, which is higher than a bottom edge of a conduction band of the semiconductor cathode of the second thyristor memory cell;
• and
• wherein a top edge of a valence band of the semiconductor anode of the second thyristor memory cell is higher than a top edge of a valence band of the first un-doped semiconductor feature of the second thyristor memory cell, which is higher than a top edge of a valence band of the second un-doped semiconductor feature of the second thyristor memory cell, which is higher than a top edge of a valence band of the semiconductor cathode of the second thyristor memory cell.

A method for fabricating a thyristor memory array, comprising steps of:

• forming a first stack feature that includes a first semiconductor layer, a first dielectric layer over the first semiconductor layer, a first sacrificial layer over the first semiconductor layer, and a second dielectric layer stacked over the first sacrificial layer and the first dielectric layer;
• forming a plurality of first holes in the first stack feature, the first holes being arranged in a first array that includes multiple columns and multiple rows, and penetrating through the second dielectric layer, the first sacrificial layer and the first dielectric layer, wherein the columns are arranged in a first direction, and the rows are arranged in a second direction that is perpendicular to the first direction;
• forming a plurality of first semiconductor stacks respectively in the first holes, each of the first semiconductor stacks including a first un-doped semiconductor layer stacked on the first semiconductor layer, a second un-doped semiconductor layer stacked on the first un-doped semiconductor layer, and a second semiconductor layer stacked on the second un-doped semiconductor layer;
• forming a plurality of first slits in the first stack feature, each of the first slits being arranged in the first direction, extending in the second direction, penetrating through at least the second dielectric layer and the first sacrificial layer, and being disposed between adjacent two of the columns of the first array;
• removing the first sacrificial layer through the first slits to partly expose the first semiconductor stacks;
• and
• forming a first gate feature on each of the first semiconductor stacks through the first slits;
• wherein a bottom edge of a conduction band of the second semiconductor layer is higher than a bottom edge of a conduction band of the first un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the first semiconductor layer;
• and
• wherein a top edge of a valence band of the second semiconductor layer is higher than a top edge of a valence band of the first un-doped semiconductor layer, which is higher than a top edge of a valence band of the second un-doped semiconductor layer, which is higher than a top edge of a valence band of the first semiconductor layer.