Partitionable digital hardware system for implementing recurrent neural networks

A digital hardware system for implementing a recurrent neural network, the digital hardware system comprising:

• at least one Legendre Memory Unit (LMU) cell computation block, each LMU cell computation block receiving input via an input bus, each LMU cell computation block comprising a digital hardware implementation of an encoder cell computation sub block set comprising one or more encoder cell computation sub blocks, a memory computation sub block set comprising one or more memory computation sub blocks, and a hidden computation sub block set comprising one or more hidden computation sub blocks;
• each encoder cell computation sub block of the encoder cell computation sub block set connected to the input bus to receive the input, each encoder cell computation sub block of the encoder cell computation sub block set connected via a first bus to receive output from the memory computation sub block set and each encoder cell computation sub block of the encoder cell computation sub block set connected via a second bus to receive output from the hidden computation sub block set;
• each memory computation sub block of the memory computation sub block set connected via a third bus to receive output from the encoder cell computation sub block set, and connected via the first bus to receive the output from the memory computation sub block set;
• each hidden computation sub block of the hidden computation sub block set connected to the input bus to receive the input, each hidden computation sub block of the hidden computation sub block set connected via the first bus to receive the output from the memory computation sub block set, and each hidden computation sub block of the hidden computation sub block set connected via the second bus to receive the output from the hidden computation sub block set,
• an output of the at least one LMU cell computation block connected to a next block of the digital hardware system.