US 12,688,346 B1Granted

Method and apparatus for mutation coverage testing with incremental sat queries

AssigneeCadence Design Systems, Inc.

InventorsGuy Wolfovitz, Ramanuj Chouksey, Amit Verma, Habeeb Anton Farah

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Abstract

A solution for performing incremental mutation coverage testing is disclosed. The solution can identify, for a cycle of a test, a first signal not covered during preceding cycles of the test and select, for the current cycle, a first value for the first signal. The solution can, responsive to the first value, determine whether the first signal is covered by the test in the current cycle and identify whether a first assertion not covered during the one or more preceding cycles is covered in the current cycle. The solution can remove the first signal from a list of signals if it determines that it is not covered by the test and remove the first assertion from a list of assertions if the first assertion is determined to be covered. The system can identify, for a next cycle, a second signal from the updated one or more signals for the circuit.

Claims20

Dependent claims

A system to perform incremental mutation coverage testing of a circuit, the system comprising:

at least one processor coupled with memory and configured to:
identify, for a current cycle of a plurality of cycles of a test for a circuit, a first signal of one or more signals for the circuit, the first signal not covered during one or more preceding cycles of the plurality of cycles;
select, for the current cycle, a first value for the first signal;
determine, in response to the first value selected for the first signal for the circuit, whether the first signal is covered by the test in the current cycle;
identify, in response to the first value selected for the first signal for the circuit, whether a first assertion of a plurality of assertions not covered during the one or more preceding cycles is covered by the test in the current cycle;
update the one or more signals to remove the first signal from the one or more signals if the first signal is determined to be covered by the test;
update the one or more assertions to remove the first assertion from the one or more assertions if the first assertion is determined to be covered by the test;
and
identify, for a next cycle following the current cycle, a second signal from the updated one or more signals for the circuit.

6 more elements

A method comprising:

determining, by at least one processor performing a current cycle of a plurality of cycles of a test for a circuit, a first signal of one or more signals for the circuit, the first signal not covered during one or more preceding cycles of the plurality of cycles;
determining, by the at least one processor for the current cycle, a first value for the first signal;
determining, by the at least one processor in response to the first value selected for the first signal for the circuit, whether the first signal is covered by the test in the current cycle;
identifying, by the at least one processor in response to the first value selected for the first signal for the circuit, whether a first assertion of a plurality of assertions not covered during the one or more preceding cycles is covered by the test in the current cycle;
updating, by the at least one processor, the one or more signals to remove the first signal from the one or more signals if the first signal is determined to be covered by the test;
updating, by the at least one processor, the one or more assertions to remove the first assertion from the one or more assertions if the first assertion is determined to be covered by the test;
and
identifying, by the at least one processor for a next cycle following the current cycle, a second signal from the updated one or more signals for the circuit.

5 more elements

Dependencies are inferred from the claim text.