Thread data race detection and synchronization for parallel implementation of verification testbenches
AssigneeSynopsys, Inc.
InventorsDawei Pan, Vivek Gaur
Life of this patent
Estimating the term…
Abstract
A testbench for a design under test (DUT) includes components used to verify functionality of the DUT through simulation of the DUT. The components are grouped into component groups, and the components within an individual component group are executed on a same thread of the simulation. The component groups are also executed on a single thread, which includes logging accesses to memory by different component groups. Based on the logged memory accesses, a processing device identifies whether any component groups create a thread data race. An action is taken in response to identifying thread data races.
Claims20
A method comprising:
- accessing a testbench for a design under test (DUT), the testbench comprising components used to verify functionality of the DUT through simulation of the DUT, wherein the components are grouped into component groups, and the components within an individual component group are executed on a same thread of the simulation;
- executing the component groups on a single thread of the simulation, comprising logging accesses to memory by different component groups during the simulation;
- identifying, by a processing device, based on the logged memory accesses from the simulation, whether any component groups create a thread data race in the simulation where component groups access same data in the simulation in a conflicting manner;
- and
- taking an action in response to identifying thread data races.
A system comprising a memory storing data and instructions and a processing device coupled with the memory and to execute the instructions;
- wherein the memory and processing device comprise:
- a description of a design under test (DUT);
- a testbench comprising components used to verify functionality of the DUT through simulation of the DUT;
- and
- a simulation environment that compiles the testbench and the DUT into executable code and runs the executable code;
- wherein running the executable code comprises:
- an initialization phase that runs the executable code on a single thread of the simulation, logs memory accesses, and identifies thread data races in the simulation from the memory accesses where components access same data in the simulation in a conflicting manner;
- and
- a run phase that runs the executable code on multiple threads.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:
- run executable code for a design under test (DUT) and corresponding testbench on a single thread of a simulation of the DUT, the testbench comprising components grouped into component groups;
- log memory accesses from the executable code during the simulation, and identify thread data races where executable code from different component groups access same data in the simulation in a conflicting manner, the thread data races identified from the memory accesses from the simulation;
- and
- automatically take action relating to the identified thread data races.
Dependencies are inferred from the claim text.