Combined divide/square root processing circuitry and method

A data processing method comprising:

• in response to a divide instruction or a square root instruction, performing a given radix-r iteration of a radix r divide operation or a given radix r iteration of a radix r square root operation using combined divide/square root processing circuitry;
• in which:
• the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix r iteration on a same data path used for both the radix r divide operation and the radix r square root operation;
• for both the radix-r divide operation and the radix-r square root operation, the combined divide/square root processing circuitry performs the given radix-r iteration by performing a plurality of radix-m sub-iterations in a same processing cycle, where m≤r;
• the shared circuitry comprises shared on-the-fly conversion circuitry which performs, in a given radix-m sub-iteration, on-the-fly conversion to generate a partial result value in a non-redundant representation;
• and
• in the given radix-m sub-iteration, the shared on-the-fly conversion circuitry is configured to select a position for inserting a next digit into the partial result value based on a mask value, for both the radix-r divide operation and the radix-r square root operation.

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• combined divide/square root processing circuitry to perform, in response to a divide instruction, a given radix r iteration of a radix r divide operation, and in response to a square root instruction, a given radix r iteration of a radix r square root operation;
• in which:
• the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix r iteration on a same data path used for both the radix r divide operation and the radix r square root operation;
• for both the radix-r divide operation and the radix-r square root operation, the combined divide/square root processing circuitry is configured to perform the given radix-r iteration by performing a plurality of radix-m sub-iterations in a same processing cycle, where m≤r;
• the shared circuitry comprises shared on-the-fly conversion circuitry to perform, in a given radix-m sub-iteration, on-the-fly conversion to generate a partial result value in a non-redundant representation;
• and
• in the given radix-m sub-iteration, the shared on-the-fly conversion circuitry is configured to select a position for inserting a next digit into the partial result value based on a mask value, for both the radix-r divide operation and the radix-r square root operation.