US 12,687,876 B2Granted

Bandgap circuit having a high-order curvature compensation current generating circuit

AssigneeKeyTek Semiconductor HongKong Limited

InventorMark A. Pinchback

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Abstract

A bandgap reference voltage generating circuit includes a bandgap cell, a tail resistor circuit, a high-order curvature compensation current generating circuit, an IZTAT current sink circuit, and a start-up circuit. The bandgap cell has a base current redistribution circuit that drives the bases of the bipolar transistors using a first base resupply current taken from the first current leg of the cell, and that uses a matched second base resupply current taken from the second current leg of the cell. VBG error due to bipolar current gain variation is reduced. The N-channel transistors of the curvature compensation current generating circuit operate in the near threshold region. The output current of the compensation circuit varies as power of approximately 2.1 of the input current. The tail resistor circuit is programmable in various ways so that the amount of curvature correction can be tailored and trimmed.

Claims22

Dependent claims

A current generating circuit, comprising:

a first current mirror formed of a first P-channel transistor, a second P channel transistor, and a third P-channel transistor, wherein a gate of the first P-channel transistor is coupled to a gate of the second P-channel transistor and to a gate of the third P-channel transistor, wherein the first current mirror supplies a first mirror output current that has a current magnitude from the first P-channel transistor, wherein the first current mirror supplies a second mirror output current that has a current magnitude from the second P-channel transistor, wherein the first current mirror supplies a third mirror output current that has a current magnitude from the third P-channel transistor, and wherein the magnitude of the second mirror output current is a fraction of the magnitude of the third mirror output current;
a ground conductor;
a first N-channel transistor having a source, a drain, and a gate, wherein the gate is coupled to the drain;
a second N-channel transistor having a source, a drain, and a gate, wherein the gate is coupled to the drain, and wherein the source of the second N-channel transistor is coupled to the drain of the first N-channel transistor, and wherein the drain of the second N-channel transistor is coupled to receive the third mirror output current from the third P-channel transistor of the first current mirror;
a third N-channel transistor having a source, a drain and a gate, wherein the gate of the third N-channel transistor is coupled to the gate of the second N-channel transistor;
a fourth N-channel transistor having a source, a drain and a gate, wherein the source of the fourth N-channel transistor is coupled to the source of the first N-channel transistor at the ground conductor, and wherein the gate of the fourth N-channel transistor is coupled to the source of the third N-channel transistor at a summing node, wherein the second P-channel transistor of the first current mirror supplies the second mirror output current to the summing node, and wherein an output current of the current generating circuit is conducted into and through the fourth N-channel transistor;
and
a sink current circuit coupled to sink a sink current from the summing node.

5 more elements

A method comprising:

(a) mirroring a first mirror current to generate a second mirror current and a third mirror current, wherein the second mirror current has a current magnitude, wherein the third mirror current has a current magnitude, wherein the current magnitude of the second mirror current is a fraction of the current magnitude of the third mirror current;
(b) conducting the third mirror current serially through a second N-channel transistor and a first N-channel transistor to a ground conductor, wherein a gate of the second N-channel transistor is coupled to a drain of the second N-channel transistor, wherein a gate of the first N-channel transistor is coupled to a drain of the first N-channel transistor, and wherein the drain of the first N-channel transistor is coupled to the source of the second N-channel transistor;
(c) conducting a first current through a third N-channel transistor onto a summing node, wherein a gate of the third N-channel transistor is coupled to the gate of the second N-channel transistor;
(d) conducting the second mirror current onto the summing node;
(e) sinking a sink current from the summing node;
and
(f) conducting an output current into a drain of a fourth N-channel transistor, wherein a gate of the fourth N-channel transistor is coupled to the summing node, and wherein a source of the fourth N-channel transistor is coupled at the ground conductor to a source of the first N-channel transistor.

4 more elements

A current generating circuit, comprising:

a current mirror that outputs a first mirror output current, a second mirror output current, and a third mirror output current, wherein a magnitude of the second mirror output current is a fraction of a magnitude of the third mirror output current;
a ground conductor;
a first diode-connected N-channel transistor and a second diode-connected N-channel transistor coupled in series to conduct the third mirror output current from the current mirror to the ground conductor;
a third N-channel transistor having a source, a drain and a gate, wherein the gate of the third N-channel transistor is coupled to a gate of the second diode-connected N-channel transistor;
a fourth N-channel transistor having a source, a drain and a gate, wherein the source of the fourth N-channel transistor is coupled to a source of the first diode-connected N-channel transistor at the ground conductor, wherein the gate of the fourth N-channel transistor is coupled to the source of the third N-channel transistor at a summing node, wherein the second mirror output current is supplied onto the summing node, and wherein an output current of the current generating circuit is conducted into and through the fourth N-channel transistor;
and
a sink current circuit coupled to sink a sink current from the summing node.

4 more elements

A bandgap reference circuit, comprising:

a bandgap cell, wherein a first mirror output current flows in a first leg of the bandgap cell, and wherein a fourth mirror output current flows in a second leg of the bandgap cell;
a current generating circuit, comprising:
a current mirror that outputs a second mirror output current and a third mirror output current, wherein a magnitude of the second mirror output current is a fraction of a magnitude of the third mirror output current;
a ground conductor;
a first diode-connected N-channel transistor and a second diode-connected N-channel transistor coupled in series to conduct the third mirror output current from the current mirror to the ground conductor;
a third N-channel transistor having a source, a drain and a gate, wherein the gate of the third N-channel transistor is coupled to a gate of the second diode-connected N-channel transistor;
a fourth N-channel transistor having a source, a drain and a gate, wherein the source of the fourth N-channel transistor is coupled to a source of the first diode-connected N-channel transistor at the ground conductor, wherein the gate of the fourth N-channel transistor is coupled to the source of the third N-channel transistor at a summing node, wherein the second mirror output current is supplied onto the summing node, and wherein an output current of the current generating circuit is conducted into and through the fourth N-channel transistor;
and
a sink current circuit coupled to sink a sink current from the summing node;
a second current mirror that mirrors the output current of the current generating circuit thereby generating a second output current;
and
a trimmable tail resistor circuit that draws a current from the bandgap cell, wherein the trimmable tail resistor circuit receives the second output current from the second current mirror.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/406,123Filed 6 Jan 2024
Published: US 2025/0224753 A110 Jul 2025
Granted: 21 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G05F 3/262
Current mirrors: using field-effect transistors only
G05F 3/267
Current mirrors: using both bipolar and field-effect technology
G05F 3/30
Using diode- transistor combinations: regulators using the difference between the base-emitter voltages of two bipolar transistors operating at…
G05F
Systems for regulating electric or magnetic variables