Overlay improvement method, and method of manufacturing semiconductor device comprising overlay improvement method

An overlay improvement method comprising:

• obtaining misalignment components of an overlay through measurement;
• converting the misalignment components into overlay parameters;
• applying a conversion logic between the overlay parameters;
• registering a target, aberration-wise control sensitivity, and the overlay parameters;
• obtaining an aberration measurement value by using an aberration sensor;
• generating a lens operating model for adjusting at least one lens of an exposure machine, based on the target, the aberration-wise control sensitivity and the aberration measurement value;
• and
• performing an exposure process by adjusting the at least one lens of the exposure machine through the lens operating model,
• wherein the overlay parameters are divided into a first overlay parameter shifting in a first direction that corresponds to an extension direction of a slit used in the exposure process, and a second overlay parameter shifting in a second direction that is perpendicular to the first direction and corresponds to a scan direction of the exposure process, and
• the performing of the exposure process comprises correcting the first overlay parameter and the second overlay parameters including a higher-order component of a 3rd order or greater with respect to a location of the slit in the first direction.

A method of manufacturing a semiconductor device, the method comprising:

• obtaining misalignment components of an overlay through measurement;
• converting the misalignment components into overlay parameters;
• applying a conversion logic between the overlay parameters;
• converting the overlay parameters, to which the conversion logic is applied, into aberration input data of an exposure machine;
• performing an exposure process on a sample wafer by applying the aberration input data to the exposure machine;
• determining whether the overlay is enhanced, based on a set criterion;
• performing the exposure process on a device wafer in response to the set criterion being satisfied;
• and
• performing a subsequent semiconductor process on the device wafer,
• wherein the overlay parameters are divided into a first overlay parameter shifting in a first direction that corresponds to an extension direction of a slit used in the exposure process, and a second overlay parameter shifting in a second direction that is perpendicular to the first direction and corresponds to a scan direction of the exposure process, and
• the performing of the exposure process on the sample wafer or the device wafer comprises correcting the first overlay parameter and the second overlay parameters including a higher-order component of a 3rd order or greater with respect to a location of the slit in the first direction.