Test method
AssigneeFuji Electric Co., Ltd.
InventorKenichi Ishii
Life of this patent
Estimating the term…
Abstract
A test method of testing a test target transistor device is provided, the test method including: arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire; and causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device. A difference between the gate voltage applied to the test transistor device and the gate voltage applied to the test target transistor device may be 5.0 V or less.
Claims21
A test method of testing a test target transistor device, comprising:
- arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire;
- and
- causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device, wherein
- the gate voltage of the test transistor device is adjustable for every test target transistor device that is the test target transistor device.
A test method of testing a test target transistor device, comprising:
- arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire;
- and
- causing a gate voltage applied to the test transistor device to be higher than a gate voltage applied to the test target transistor device, wherein
- the gate voltage of the test transistor device is controlled based on a size of a pad of the test target transistor device.
A test method of testing a test target transistor device, comprising:
- arranging the test target transistor device and a test transistor device in series between a high voltage side wire and a low voltage side wire;
- and
- causing a gate voltage applied to the test transistor device to control the test transistor device to be in an ON state to be higher than a gate voltage applied to the test target transistor device to control the test target transistor device to be in an ON state, wherein the testing is for a short circuit,
- wherein the gate voltage of the test transistor device is adjustable for every test target transistor device that is the test target transistor device.
Dependencies are inferred from the claim text.