Systems and methods for mitigating stimulation current spikes and glitches in neurostimulation systems
AssigneeAdvanced Neuromodulation Systems, Inc.
InventorSteven Boor
Life of this patent
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Abstract
The present disclosure provides systems and methods for mitigating stimulation pulse glitches when a voltage multiplier is stepped during delivery of stimulation current to a patient. An implantable pulse generator (IPG) includes pulse generating circuitry configured to generate stimulation pulses to be applied to a patient at an output of the IPG, voltage multiplier circuitry configured to step an output voltage to an anode of the pulse generating circuitry, and glitch mitigating circuitry configured to mitigate current glitches generated when the output voltage is stepped during generation of a stimulation pulse.
Claims17
An implantable pulse generator (IPG) for use in a neurostimulation system, the IPG comprising:
- a case;
- pulse generating circuitry configured to generate stimulation pulses to be applied to a patient at an output of the IPG;
- voltage multiplier circuitry configured to step an output voltage to an anode of the pulse generating circuitry;
- and
- glitch mitigating circuitry configured to mitigate current glitches generated when the output voltage is stepped during generation of a stimulation pulse to be applied to the patient, wherein the glitch mitigating circuitry comprises:
- a first step switch connected to the case;
- a second step switch connected to a cathode of the pulse generating circuitry;
- a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position;
- and
- a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.
A neurostimulation system comprising:
- an implantable stimulation lead comprising a plurality of contacts;
- and
- an implantable pulse generator (IPG) communicatively coupled to the implantable stimulation lead, the IPG comprising:
- a case;
- pulse generating circuitry configured to generate stimulation pulses to be applied to a patient through the implantable stimulation lead;
- voltage multiplier circuitry configured to step an output voltage to an anode of the pulse generating circuitry;
- and
- glitch mitigating circuitry configured to mitigate current glitches generated when the output voltage is stepped during generation of a stimulation pulse to be applied to the patient, wherein the glitch mitigation circuitry comprises:
- a first step switch connected to the case:
- a second step switch connected to a cathode of the pulse generating circuitry;
- a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position;
- and
- a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.
A method of applying neurostimulation, the method comprising:
- generating, using an implantable pulse generator (IPG), a pulse to be delivered to a patient, wherein the IPG includes a case;
- stepping an output voltage to an anode of the IPG while the pulse is being delivered to the patient;
- and
- mitigating, using glitch mitigation circuitry, a current glitch generated by the stepped output voltage during generation of a pulse to be delivered to the patient, wherein the glitch mitigation circuitry comprises:
- a first step switch connected to the case;
- a second step switch connected to a cathode of the pulse generating circuitry;
- a first glitch mitigation capacitor connected to the first step switch, wherein the first glitch mitigation capacitor is connected to the case and the anode when the first step switch is in a closed position;
- and
- a second glitch mitigation capacitor connected to the second step switch, wherein the second glitch mitigation capacitor is connected to the cathode and the anode when the second step switch is in a closed position.
Dependencies are inferred from the claim text.