Package architecture with memory chips having different process regions

An IC structure, comprising:

• a substrate;
• a first portion comprising a first active region and a first backend region;
• and
• a second portion comprising a second active region and a second backend region,
• wherein:
• the first portion is in contact with the second portion along an interface,
• the first active region and the second active region are in the substrate,
• the first active region comprises transistors that are larger than transistors in the second active region,
• the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region, and
• the IC structure is part of an IC die embedded in an interposer comprising organic dielectric material.

An IC structure, comprising:

• a substrate having a first side and a second side;
• a first portion comprising a first active region and a first backend region;
• and
• a second portion comprising a second active region and a second backend region,
• wherein:
• the first portion is on the first side of the substrate,
• the second portion is on the second side of the substrate,
• the first active region comprises transistors that are larger than transistors in the second active region,
• the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region, and
• the IC structure is part of an IC die embedded in an interposer comprising organic dielectric material.