Semiconductor package and method for manufacturing the semiconductor package

A semiconductor package comprising:

• a substrate;
• a circuit layer disposed on a lower surface of the substrate, the circuit layer comprising an interconnection structure and an interlayer insulating layer surrounding the interconnection structure;
• a first redistribution structure disposed adjacent to the circuit layer on the lower surface of the substrate, the first redistribution structure comprising a first redistribution layer and a first redistribution insulating layer surrounding the first redistribution layer;
• a connection insulating layer having an upper surface contacting a lower surface of the first redistribution insulating layer and a lower surface of the interlayer insulating layer;
• a semiconductor chip disposed below the first redistribution structure and electrically connected to the first redistribution layer;
• an underfill layer disposed between the first redistribution structure and the semiconductor chip;
• a first vertical connection structure disposed on a lower surface of the circuit layer;
• a second vertical connection structure disposed on a lower surface of the connection insulating layer;
• and
• a second redistribution structure disposed below the first vertical connection structure and the second vertical connection structure, the second redistribution structure comprising a second redistribution layer,
• wherein the interlayer insulating layer and the first redistribution insulating layer comprise different materials.

A semiconductor package, comprising:

• a substrate;
• a circuit layer disposed on a lower surface of the substrate, the circuit layer comprising an interconnection structure;
• a first redistribution structure disposed adjacent to the circuit layer on the lower surface of the substrate, the first redistribution structure comprising a first redistribution layer;
• a connection structure comprising:
• a connection interconnection electrically connected to the interconnection structure and the first redistribution layer;
• and
• a connection insulating layer covering the connection interconnection;
• a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer;
• a first vertical connection structure disposed on a lower surface of the circuit layer;
• a second vertical connection structure disposed on a lower surface of the connection structure;
• and
• a second redistribution structure disposed below the first and second vertical connection structures, the second redistribution structure comprising a second redistribution layer,
• wherein the second vertical connection structure contacts the connection insulating layer, and is electrically connected to the second redistribution layer.