Semiconductor device package with wettable flanks

A method, comprising:

• placing a partially etched leadframe with a board side surface of the leadframe facing a support, the partially etched leadframe including unit leadframe devices spaced by saw streets and having terminals with a device side surface opposite the board side surface on an upper layer, and the board side surface on a lower layer extending from the upper layer, a first exterior end of the terminals formed on the upper layer, and the terminals with a planar surface on the lower layer on the board side surface, and a second exterior end of the terminals formed on the lower layer, the second exterior end inset from the first exterior end of the terminals by an inset portion;
• flip chip mounting semiconductor dies on the device side surface of the unit leadframe devices, conductive post connects extending from the semiconductor dies to the device side surface of the terminals, and forming solder joints to the conductive post connects;
• covering the semiconductor die, the partially etched leadframe and portions of the terminals with mold compound to form semiconductor device packages, the mold compound covering the second exterior end of the terminals and the inset portion of the terminals, the board side surface of the terminals exposed from the mold compound;
• selectively using a laser on the board side surface of the unit leadframe devices, removing the mold compound from the second exterior end of the terminals and the inset portion of the terminals to form wettable flanks with the inset portion and the second exterior end exposed to form a stepped edge;
• and
• cutting along the saw streets to separate unit semiconductor device packages on the partially etched leadframe from one another.

A no-lead semiconductor device package, comprising:

• a die pad in a central portion of a partially etched leadframe, the die pad having a device side surface and an opposite board side surface;
• terminals spaced from the die pad, the terminals comprising:
• a device side surface formed in an upper layer of the partially etched leadframe, and a first exterior end in the upper layer of the partially etched leadframe;
• a board side surface formed in a lower layer of the partially etched leadframe extending from the upper layer, the board side surface of the terminal opposite the device side surface;
• a second exterior end in the lower layer of the partially etched leadframe, the second exterior end inset from the first exterior end, and
• an inset portion extending from the first exterior end to the second exterior end, a plane along a surface of the inset portion parallel to a plane along the board side surface;
• a semiconductor die mounted to the device side surface of the die pad by die attach material and having bond pads on a device side surface facing away from the die pad;
• wire bonds connecting bond pads of the semiconductor die to the device side surface of the terminals;
• and
• mold compound covering the semiconductor die, the die pad, and the wire bonds, the second exterior end of the terminals and the inset portion of the terminals exposed from the mold compound, with the inset portion and the second exterior end forming a stepped edge, with mold compound extending along sides of the terminals.

A no-lead semiconductor device package, comprising:

• a partially etched leadframe including terminals, the terminals comprising:
• a device side surface formed in an upper layer of the partially etched leadframe, and a first exterior end in the upper layer of the partially etched leadframe;
• a board side surface formed in a lower layer of the partially etched leadframe extending from the upper layer, the board side surface of the terminal opposite the device side surface;
• a second exterior end in the lower layer of the partially etched leadframe, the second exterior end inset from the first exterior end, and
• an inset portion extending from the first exterior end to the second exterior end, a plane along a surface of the second exterior end parallel to a plane along a surface of the first exterior end;
• a semiconductor die flip chip mounted to the device side surface of the terminals by solder joints between post connects extending from bond pads on the semiconductor die and the device side surface of the terminals;
• and
• mold compound covering the semiconductor die and portions of the terminals, with the second exterior end of the terminals and the inset portion of the terminals exposed from the mold compound to form wettable flanks with the inset portion and the second end forming stepped edges on the terminals, with mold compound extending along the sides of the terminals.