Delamination/cracking improvement at solder joints in microelectronics package

Abstract

The present disclosure relates to a microelectronics package with significantly reduced delamination/cracking at solder joints, and a process for making the same. The disclosed microelectronics package includes a carrier, a solder joint region over the carrier, a top intermetallic (IMC) layer over the solder joint region, and a device die over the top IMC layer. Herein, the device die includes a substrate, an active device over the substrate, a top barrier layer underneath the substrate, and a backside metal layer vertically between the top IMC layer and the top barrier layer. The backside metal layer is formed of gold (Au) with a thickness at least 0.5 μm. The top IMC layer comprises gold nickel tin (AuNiSn) or gold platinum tin (AuPtSn), and the solder joint region comprises an Au-rich gold-tin (Au5Sn) and gold-tin (AuSn) eutectic mixture.

Dependencies are inferred from the claim text.