Semiconductor package

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip on the package substrate;
• a bonding enhancing layer on an upper portion of the semiconductor chip;
• a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip;
• a thermal interface material layer on the bonding enhancing layer and in a gap between the semiconductor chip and the heat dissipation member, wherein the thermal interface material layer comprises a liquid metal;
• and
• a porous barrier structure on side surfaces of the bonding enhancing layer and the thermal interface material layer, wherein the porous barrier structure comprises a metal material and air permeable pores and surrounds the side surfaces of the bonding enhancing layer and the thermal interface material layer,
• wherein the thermal interface material layer does not extend into the air permeable pores of the porous barrier structure.

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip on the package substrate;
• a heat dissipation member on the semiconductor chip and spaced apart from the semiconductor chip;
• a bonding enhancing layer on the semiconductor chip;
• a thermal interface material layer in a gap between the semiconductor chip and the bonding enhancing layer, the thermal interface material layer comprising a liquid metal;
• and
• a porous barrier structure comprising a metal material on side surfaces of the bonding enhancing layer and the thermal interface material layer,
• wherein the porous barrier structure surrounds the side surfaces of the bonding enhancing layer and the thermal interface material layer.