Forming method of interconnect structure
AssigneeHon Hai Precision Industry Co., Ltd.
InventorsYun-Hung Shen, Chien-Jung Yang
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Abstract
The present disclosure provides a forming method of an interconnect structure. The method includes forming a multilayer stack on a substrate including a wiring layer, where the multilayer stack includes an extreme low-k dielectric layer above the wiring layer and a mask layer above the extreme low-k dielectric layer. The method also includes etching the multilayer stack to form a trench exposing the extreme low-k dielectric layer, forming a spacer on a sidewall of the trench to apply a tensile stress to the mask layer, etching the extreme low-k dielectric layer to form a via hole exposing the wiring layer, filling the trench and the via hole with a conductive material, and performing a planarization process on the multilayer stack to remove the spacer.
Claims20
A method of forming an interconnect structure, comprising:
- forming a multilayer stack on a substrate comprising a wiring layer, wherein the multilayer stack comprises:
- an extreme low-k dielectric layer above the wiring layer;
- and
- a mask layer above the extreme low-k dielectric layer;
- etching the multilayer stack to form a trench, wherein the trench exposes the extreme low-k dielectric layer;
- forming a spacer on a sidewall of the trench, wherein the spacer physically contacts the mask layer;
- etching the extreme low-k dielectric layer to form a via hole, wherein the via hole exposes the wiring layer;
- filling the trench and the via hole with a conductive material;
- and
- performing a planarization process on the multilayer stack to remove the spacer.
A method of forming an interconnect structure, comprising:
- forming an extreme low-k dielectric layer above a substrate comprising a wiring layer;
- performing a first deposition process to form a first titanium nitride layer above the extreme low-k dielectric layer;
- performing a first etching process to form a first trench in the first titanium nitride layer and the extreme low-k dielectric layer;
- performing a second deposition process to form a second titanium nitride layer on a sidewall of the first trench;
- performing a second etching process to form a via hole in the extreme low-k dielectric layer, wherein the via hole exposes the wiring layer;
- filling the first trench and the via hole with a conductive material;
- and
- removing the first titanium nitride layer and the second titanium nitride layer.
Dependencies are inferred from the claim text.