Low-stress dielectric layer, planarization method, and low-temperature processing for 3D-integrated electrical device

A three-dimensional (3D)-integrated electrical device comprising:

• a first electrical device;
• and
• a second electrical device comprising a read out integrated circuit;
• wherein the first electrical device is bonded and electrically integrated to the second electrical device;
• and
• wherein the first electrical device comprises:
• a substrate;
• a low-stress dielectric layer having a first side and a second side, the low-stress dielectric layer supported by the substrate, wherein the low-stress dielectric layer has a via hole, and wherein the first side of the low-stress dielectric layer faces away from the substrate;
• an electrically conductive vertical interconnect disposed in the via hole, the electrically conductive vertical interconnect extending towards the second side of the low-stress dielectric layer;
• and
• a fragile material disposed under the second side of the low-stress dielectric layer;
• wherein the electrically conductive vertical interconnect is diffusion bonded to another opposing interconnect at a temperature of 150° C. or less;
• wherein an upper surface of the first electrical device is substantially planar along a plane and includes an upper surface of the electrically conductive vertical interconnect and an upper surface of the low-stress dielectric layer separated by a base layer along the plane;
• wherein, prior to diffusion bonding of the electrically conductive vertical interconnect to the other opposing interconnect, the electrically conductive vertical interconnect has a dished surface creating a gap between the electrically conductive vertical interconnect and the other opposing interconnect;
• wherein the gap between the electrically conductive vertical interconnect and the other opposing interconnect is closed as a result of the electrically conductive vertical interconnect expanding to fill the gap during diffusion bonding;
• wherein the electrically conductive vertical interconnect has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the low-stress dielectric layer;
• and
• wherein any stress imparted to the fragile material by the low-stress dielectric layer during diffusion bonding is less than a failure stress of the fragile material.

A method of fabricating an electrical device, comprising:

• forming a fragile material over at least a portion of a substrate;
• forming a low-stress dielectric layer having a first side and a second side, the low-stress dielectric layer overlying at least a portion of the fragile material, wherein the first side of the low-stress dielectric layer faces away from the substrate;
• forming a via hole in the low-stress dielectric layer;
• and
• forming an electrically conductive vertical interconnect in the via hole, the electrically conductive vertical interconnect extending towards the second side of the low-stress dielectric layer;
• wherein the electrically conductive vertical interconnect is diffusion bonded to another opposing interconnect at a temperature of 150° C. or less;
• wherein an upper surface of the electrical device is substantially planar along a plane and includes an upper surface of the electrically conductive vertical interconnect and an upper surface of the low-stress dielectric layer separated by a base layer along the plane;
• wherein, prior to diffusion bonding of the electrically conductive vertical interconnect to the other opposing interconnect, the electrically conductive vertical interconnect has a dished surface creating a gap between the electrically conductive vertical interconnect and the other opposing interconnect;
• wherein the gap between the electrically conductive vertical interconnect and the other opposing interconnect is closed as a result of the electrically conductive vertical interconnect expanding to fill the gap during diffusion bonding;
• wherein the electrically conductive vertical interconnect has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the low-stress dielectric layer;
• and
• wherein any stress imparted to the fragile material by the low-stress dielectric layer during diffusion bonding is less than a failure stress of the fragile material.