Self-aligned backside interconnect structures

A semiconductor structure, comprising:

• a first plurality of backside power rail interconnects located within a first cell height region of a substrate;
• a second plurality of backside power rail interconnects located within a second cell height region of the substrate;
• a first isolation region located between the first cell height region of the substrate and the second cell height region of the substrate, the first isolation region electrically separating the first cell height region and the second cell height region;
• and
• a second isolation region located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects, the second isolation region electrically separating the adjacent power rail interconnects,
• wherein the first plurality of backside power rail interconnects and the second plurality of backside power rail interconnects connect with a plurality of backside power rails, and the plurality of backside power rails form a grid shape separated by the first isolation region and the second isolation region.