Power semiconductor device and method for fabricating the same
AssigneesHyundai Motor Company, Kia Corporation
InventorJong Seok Lee
Life of this patent
Estimating the term…
Abstract
A power semiconductor device includes a semiconductor layer, a well region located inside the semiconductor layer and having a first conductivity type, a source region located on the well region and having a second conductivity type, a gate region in contact with a side surface of the well region and surrounding the well region, a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type, and a contact region located on the well region and having the first conductivity type. The drift region includes a protruding region in contact with another side surface of the well region. The power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region.
Claims8
A power semiconductor device comprising:
- a semiconductor layer;
- a well region located inside the semiconductor layer and having a first conductivity type;
- a source region located on the well region and having a second conductivity type;
- a gate region in contact with a side surface of the well region and surrounding the well region;
- a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type;
- a contact region located on the well region and having the first conductivity type;
- and
- a first channel region and a second channel region located in a region where the gate region and the well region are in contact with each other,
- wherein the drift region includes a protruding region in contact with another side surface of the well region,
- wherein the power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region,
- wherein the first channel region includes a horizontal channel extending from the source region toward the protruding region, and
- wherein the second channel region includes a vertical channel extending from the source region along a side surface of the gate region.
A power semiconductor device comprising:
- a semiconductor layer;
- a well region located inside the semiconductor layer and having a first conductivity type;
- a source region located on the well region and having a second conductivity type;
- a gate region in contact with a side surface of the well region and surrounding the well region;
- a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type;
- and
- a contact region located on the well region and having the first conductivity type,
- wherein the drift region includes a protruding region in contact with another side surface of the well region,
- wherein the power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region, and
- wherein the gate region is in contact with the well region on at least three surfaces.
A power semiconductor device comprising:
- a semiconductor layer;
- a well region located inside the semiconductor layer and having a first conductivity type;
- a source region located on the well region and having a second conductivity type;
- a gate region in contact with a side surface of the well region and surrounding the well region;
- a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type;
- and
- a contact region located on the well region and having the first conductivity type,
- wherein the drift region includes a protruding region in contact with another side surface of the well region,
- wherein the power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region,
- wherein the well region is located at a first depth from one surface of the semiconductor layer,
- wherein the gate region is located at a second depth from the one surface of the semiconductor layer,
- wherein the first depth is greater than the second depth, and
- wherein the well region includes an extended region extending along the bottom surface of the gate region.
Dependencies are inferred from the claim text.