Back to results
US 12,684,824 B2Granted
Integrated circuits with self-aligned tub architecture
AssigneeIntel Corporation
InventorsDan S. Lavric, YenTing Chiu, Mohit K. Haran, Allen B. Gardiner, Leonard P. Guler, Andy Chih-Hung Wei, Tahir Ghani
Life of this patent
Estimating the term…
Abstract
Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.
Claims11
An integrated circuit structure, comprising:
- an n-channel metal oxide semiconductor (NMOS) transistor having a gate stack, wherein NMOS transistor comprises a first plurality of silicon nano-ribbons;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate stack, wherein the PMOS transistor comprises a second plurality of silicon nano-ribbons;
- a bottom gate layer;
- a first gate wall coupled to the bottom gate layer;
- a second gate wall coupled to the bottom gate layer;
- a third gate wall coupled to the bottom gate layer, wherein the gate stack of the NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, the gate stack of the PMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall, and the first, second, and third gate walls have a common height from the bottom gate layer;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons, wherein the WFM layer or dipole layer is further coupled to at least a portion of the first gate wall and the second gate wall.
5 more elements
An integrated circuit structure, comprising:
- a first n-channel metal oxide semiconductor (NMOS) transistor having a gate stack, wherein first NMOS transistor comprises a first plurality of silicon nano-ribbons;
- a second NMOS transistor having a gate stack, wherein the second NMOS transistor comprises a second plurality of silicon nano-ribbons;
- a first p-channel metal oxide semiconductor (PMOS) transistor having a gate stack;
- a second PMOS transistor having a gate stack;
- a bottom gate layer;
- a first gate wall coupled to the bottom gate layer;
- a second gate wall coupled to the bottom gate layer;
- a third gate wall coupled to the bottom gate layer;
- a fourth gate wall coupled to the bottom gate layer;
- a fifth gate wall coupled to the bottom gate layer, wherein the gate stack of the first NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, the gate stack of the second NMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall, the gate stack of the first PMOS transistor is disposed between and is in contact with the third gate wall and the fourth gate wall, the gate stack of the second PMOS transistor is disposed between and is in contact with the fourth gate wall and the fifth gate wall, and the first, second, third, fourth, and fifth gate walls have a common height from the bottom gate layer;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons and the second plurality of silicon nano-ribbons, wherein the WFM layer or dipole layer is further coupled to at least a portion of one of:
- the first gate wall, the second gate wall, the third gate wall, or the fourth gate wall.
10 more elements
A computing device, comprising:
- a board;
- and
- a component coupled to the board, the component including an integrated circuit structure, comprising:
- an n-channel metal oxide semiconductor (NMOS) transistor having a gate stack, wherein NMOS transistor comprises a first plurality of silicon nano-ribbons;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate stack, wherein the PMOS transistor comprises a second plurality of silicon nano-ribbons;
- a bottom gate layer;
- a first gate wall coupled to the bottom gate layer;
- a second gate wall coupled to the bottom gate layer;
- a third gate wall coupled to the bottom gate layer, wherein the gate stack of the NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, the gate stack of the PMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall, and the first, second, and third gate walls have a common height from the bottom gate layer;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons, wherein the WFM layer or dipole layer is further coupled to at least a portion of the first gate wall and the second gate wall.
8 more elements
A computing device, comprising:
- a board;
- and
- a component coupled to the board, the component including an integrated circuit structure, comprising:
- a first n-channel metal oxide semiconductor (NMOS) transistor having a gate stack, wherein first NMOS transistor comprises a first plurality of silicon nano-ribbons;
- a second NMOS transistor having a gate stack, wherein the second NMOS transistor comprises a second plurality of silicon nano-ribbons;
- a first p-channel metal oxide semiconductor (PMOS) transistor having a gate stack;
- a second PMOS transistor having a gate stack;
- a bottom gate layer;
- a first gate wall coupled to the bottom gate layer;
- a second gate wall coupled to the bottom gate layer;
- a third gate wall coupled to the bottom gate layer;
- a fourth gate wall coupled to the bottom gate layer;
- a fifth gate wall coupled to the bottom gate layer, wherein the gate stack of the first NMOS transistor is disposed between and is in contact with the first gate wall and the second gate wall, the gate stack of the second NMOS transistor is disposed between and is in contact with the second gate wall and the third gate wall, the gate stack of the first PMOS transistor is disposed between and is in contact with the third gate wall and the fourth gate wall, the gate stack of the second PMOS transistor is disposed between and is in contact with the fourth gate wall and the fifth gate wall, and the first, second, third, fourth, and fifth gate walls have a common height from the bottom gate layer;
- and
- a work function metal (WFM) layer or dipole layer coupled to the first plurality of silicon nano-ribbons and the second plurality of silicon nano-ribbons, wherein the WFM layer or dipole layer is further coupled to at least a portion of one of:
- the first gate wall, the second gate wall, the third gate wall, or the fourth gate wall.
13 more elements
Dependencies are inferred from the claim text.